blob: 783705dffef14cd6b52daa32a5213bb5323ca117 [file] [log] [blame]
Patrick Georgi4d6ad832015-06-22 19:43:18 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2015 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Patrick Georgi4d6ad832015-06-22 19:43:18 +020014 */
15
16#include <arch/io.h>
17#include <bootblock_common.h>
18#include <console/console.h>
19#include <device/i2c.h>
20#include <soc/addressmap.h>
21#include <soc/clk_rst.h>
22#include <soc/clock.h>
23#include <soc/funitcfg.h>
24#include <soc/nvidia/tegra/i2c.h>
25#include <soc/padconfig.h>
26#include <soc/pmc.h>
27#include <soc/power.h>
28#include <soc/spi.h>
29
30#include "pmic.h"
31
32/********************** PMIC **********************************/
33static const struct pad_config pmic_pads[] = {
34 PAD_CFG_SFIO(PWR_I2C_SCL, PINMUX_INPUT_ENABLE, I2CPMU),
35 PAD_CFG_SFIO(PWR_I2C_SDA, PINMUX_INPUT_ENABLE, I2CPMU),
36};
37
38/********************** SPI Flash *****************************/
39static const struct pad_config spiflash_pads[] = {
40 /* QSPI fLash: mosi, miso, clk, cs0, hold, wp */
Furquan Shaikhe431ab92015-07-13 09:46:56 -070041 PAD_CFG_SFIO(QSPI_IO0, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP |
42 PINMUX_DRIVE_2X, QSPI),
43 PAD_CFG_SFIO(QSPI_IO1, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP |
44 PINMUX_DRIVE_2X, QSPI),
45 PAD_CFG_SFIO(QSPI_SCK, PINMUX_INPUT_ENABLE | PINMUX_DRIVE_2X, QSPI),
46 PAD_CFG_SFIO(QSPI_CS_N, PINMUX_INPUT_ENABLE | PINMUX_DRIVE_2X, QSPI),
47 PAD_CFG_SFIO(QSPI_IO2, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP |
48 PINMUX_DRIVE_2X, QSPI),
49 PAD_CFG_SFIO(QSPI_IO3, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP |
50 PINMUX_DRIVE_2X, QSPI),
Patrick Georgi4d6ad832015-06-22 19:43:18 +020051};
52
53/********************* TPM ************************************/
54static const struct pad_config tpm_pads[] = {
55 PAD_CFG_SFIO(GEN3_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3),
56 PAD_CFG_SFIO(GEN3_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3),
57};
58
59/********************* EC *************************************/
60static const struct pad_config ec_i2c_pads[] = {
61 PAD_CFG_SFIO(GEN2_I2C_SCL, PINMUX_INPUT_ENABLE, I2C2),
62 PAD_CFG_SFIO(GEN2_I2C_SDA, PINMUX_INPUT_ENABLE, I2C2),
63};
64
65/********************* Funits *********************************/
66static const struct funit_cfg funits[] = {
67 /* PMIC on I2C5 (PWR_I2C* pads) at 400kHz. */
68 FUNIT_CFG(I2C5, PLLP, 400, pmic_pads, ARRAY_SIZE(pmic_pads)),
69 /* SPI flash at 24MHz on QSPI controller. */
70 FUNIT_CFG(QSPI, PLLP, 24000, spiflash_pads, ARRAY_SIZE(spiflash_pads)),
71 /* TPM on I2C3 @ 400kHz */
72 FUNIT_CFG(I2C3, PLLP, 400, tpm_pads, ARRAY_SIZE(tpm_pads)),
73 /* EC on I2C2 - pulled to 3.3V @ 100kHz */
74 FUNIT_CFG(I2C2, PLLP, 100, ec_i2c_pads, ARRAY_SIZE(ec_i2c_pads)),
75};
76
77/********************* UART ***********************************/
78static const struct pad_config uart_console_pads[] = {
79 /* UARTA: tx, rx, rts, cts */
80 PAD_CFG_SFIO(UART1_TX, PINMUX_PULL_NONE, UARTA),
81 PAD_CFG_SFIO(UART1_RX, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, UARTA),
82 PAD_CFG_SFIO(UART1_RTS, PINMUX_PULL_UP, UARTA),
83 PAD_CFG_SFIO(UART1_CTS, PINMUX_PULL_UP, UARTA),
84};
85
86void bootblock_mainboard_early_init(void)
87{
88 soc_configure_pads(uart_console_pads, ARRAY_SIZE(uart_console_pads));
89}
90
91static void set_clock_sources(void)
92{
93 /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
94 write32(CLK_RST_REG(clk_src_uarta), PLLP << CLK_SOURCE_SHIFT);
95}
96
97/********************* PADs ***********************************/
98static const struct pad_config padcfgs[] = {
99 /* Board build id bits 1:0 */
100 PAD_CFG_GPIO_INPUT(GPIO_PK1, PINMUX_PULL_NONE),
101 PAD_CFG_GPIO_INPUT(GPIO_PK0, PINMUX_PULL_NONE),
102};
103
104void bootblock_mainboard_init(void)
105{
106 set_clock_sources();
107
108 /* Set up the pads required to load romstage. */
109 soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
110 soc_configure_funits(funits, ARRAY_SIZE(funits));
111
112 /* PMIC */
113 i2c_init(I2CPWR_BUS);
114 pmic_init(I2CPWR_BUS);
115
116 /* TPM */
117 i2c_init(I2C3_BUS);
118
119 /* EC */
120 i2c_init(I2C2_BUS);
121
122 /*
123 * Set power detect override for GPIO, audio & sdmmc3 rails.
124 * GPIO rail override is required to put it into 1.8V mode.
125 */
126 pmc_override_pwr_det(PMC_GPIO_RAIL_AO_MASK | PMC_AUDIO_RAIL_AO_MASK |
127 PMC_SDMMC3_RAIL_AO_MASK, PMC_GPIO_RAIL_AO_DISABLE |
128 PMC_AUDIO_RAIL_AO_DISABLE |
129 PMC_SDMMC3_RAIL_AO_DISABLE);
130}