Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright 2013 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
| 18 | #include <console/console.h> |
| 19 | #include <cpu/x86/smm.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 20 | #include <soc/pm.h> |
| 21 | #include <soc/smm.h> |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 22 | #include <elog.h> |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 23 | #include <ec/google/chromeec/ec.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 24 | #include <soc/gpio.h> |
| 25 | #include <soc/iomap.h> |
| 26 | #include <soc/nvs.h> |
| 27 | #include <soc/pm.h> |
| 28 | #include <soc/smm.h> |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 29 | #include "ec.h" |
Duncan Laurie | 1247b87 | 2014-09-29 08:35:29 -0700 | [diff] [blame] | 30 | #include "gpio.h" |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 31 | |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 32 | static u8 mainboard_smi_ec(void) |
| 33 | { |
| 34 | u8 cmd = google_chromeec_get_event(); |
| 35 | u32 pm1_cnt; |
| 36 | |
| 37 | #if CONFIG_ELOG_GSMI |
| 38 | /* Log this event */ |
| 39 | if (cmd) |
| 40 | elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); |
| 41 | #endif |
| 42 | |
| 43 | switch (cmd) { |
| 44 | case EC_HOST_EVENT_LID_CLOSED: |
| 45 | printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); |
| 46 | |
| 47 | /* Go to S5 */ |
Duncan Laurie | 2663a55 | 2014-05-14 15:59:37 -0700 | [diff] [blame] | 48 | pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 49 | pm1_cnt |= (0xf << 10); |
Duncan Laurie | 2663a55 | 2014-05-14 15:59:37 -0700 | [diff] [blame] | 50 | outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 51 | break; |
| 52 | } |
| 53 | |
| 54 | return cmd; |
| 55 | } |
| 56 | |
| 57 | /* gpi_sts is GPIO 47:32 */ |
| 58 | void mainboard_smi_gpi(u32 gpi_sts) |
| 59 | { |
| 60 | if (gpi_sts & (1 << (EC_SMI_GPI - 32))) { |
| 61 | /* Process all pending events */ |
| 62 | while (mainboard_smi_ec() != 0); |
| 63 | } |
| 64 | } |
| 65 | |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 66 | void mainboard_smi_sleep(u8 slp_typ) |
| 67 | { |
| 68 | /* Disable USB charging if required */ |
| 69 | switch (slp_typ) { |
| 70 | case 3: |
Duncan Laurie | 2663a55 | 2014-05-14 15:59:37 -0700 | [diff] [blame] | 71 | if (smm_get_gnvs()->s3u0 == 0) { |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 72 | google_chromeec_set_usb_charge_mode( |
| 73 | 0, USB_CHARGE_MODE_DISABLED); |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 74 | google_chromeec_set_usb_charge_mode( |
| 75 | 1, USB_CHARGE_MODE_DISABLED); |
Duncan Laurie | 2663a55 | 2014-05-14 15:59:37 -0700 | [diff] [blame] | 76 | } |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 77 | |
Duncan Laurie | 5106b9d | 2014-06-10 10:05:03 -0700 | [diff] [blame] | 78 | /* Put SSD in reset to prevent leak. */ |
Duncan Laurie | 1247b87 | 2014-09-29 08:35:29 -0700 | [diff] [blame] | 79 | set_gpio(SAMUS_GPIO_SSD_RESET_L, 0); |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 80 | /* Prevent leak from standby rail to WLAN rail in S3. */ |
Duncan Laurie | 1247b87 | 2014-09-29 08:35:29 -0700 | [diff] [blame] | 81 | set_gpio(SAMUS_GPIO_WLAN_DISABLE_L, 0); |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 82 | /* Disable LTE */ |
Duncan Laurie | 1247b87 | 2014-09-29 08:35:29 -0700 | [diff] [blame] | 83 | set_gpio(SAMUS_GPIO_LTE_DISABLE_L, 0); |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 84 | |
| 85 | /* Enable wake events */ |
| 86 | google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); |
| 87 | break; |
| 88 | case 5: |
Duncan Laurie | 2663a55 | 2014-05-14 15:59:37 -0700 | [diff] [blame] | 89 | if (smm_get_gnvs()->s5u0 == 0) { |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 90 | google_chromeec_set_usb_charge_mode( |
| 91 | 0, USB_CHARGE_MODE_DISABLED); |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 92 | google_chromeec_set_usb_charge_mode( |
| 93 | 1, USB_CHARGE_MODE_DISABLED); |
Duncan Laurie | 2663a55 | 2014-05-14 15:59:37 -0700 | [diff] [blame] | 94 | } |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 95 | |
Duncan Laurie | 5106b9d | 2014-06-10 10:05:03 -0700 | [diff] [blame] | 96 | /* Put SSD in reset to prevent leak. */ |
Duncan Laurie | 1247b87 | 2014-09-29 08:35:29 -0700 | [diff] [blame] | 97 | set_gpio(SAMUS_GPIO_SSD_RESET_L, 0); |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 98 | /* Prevent leak from standby rail to WLAN rail in S5. */ |
Duncan Laurie | 1247b87 | 2014-09-29 08:35:29 -0700 | [diff] [blame] | 99 | set_gpio(SAMUS_GPIO_WLAN_DISABLE_L, 0); |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 100 | /* Disable LTE */ |
Duncan Laurie | 1247b87 | 2014-09-29 08:35:29 -0700 | [diff] [blame] | 101 | set_gpio(SAMUS_GPIO_LTE_DISABLE_L, 0); |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 102 | |
| 103 | /* Enable wake events */ |
| 104 | google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); |
| 105 | break; |
| 106 | } |
| 107 | |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 108 | /* Disable SCI and SMI events */ |
| 109 | google_chromeec_set_smi_mask(0); |
| 110 | google_chromeec_set_sci_mask(0); |
| 111 | |
| 112 | /* Clear pending events that may trigger immediate wake */ |
| 113 | while (google_chromeec_get_event() != 0); |
| 114 | } |
| 115 | |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 116 | int mainboard_smi_apmc(u8 apmc) |
| 117 | { |
| 118 | switch (apmc) { |
Duncan Laurie | ddc3e42 | 2013-10-02 16:10:54 -0700 | [diff] [blame] | 119 | case APM_CNT_ACPI_ENABLE: |
| 120 | google_chromeec_set_smi_mask(0); |
| 121 | /* Clear all pending events */ |
| 122 | while (google_chromeec_get_event() != 0); |
| 123 | google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); |
| 124 | break; |
| 125 | case APM_CNT_ACPI_DISABLE: |
| 126 | google_chromeec_set_sci_mask(0); |
| 127 | /* Clear all pending events */ |
| 128 | while (google_chromeec_get_event() != 0); |
| 129 | google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); |
| 130 | break; |
| 131 | } |
| 132 | return 0; |
| 133 | } |