Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <string.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 17 | #include <soc/spi.h> |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 18 | |
| 19 | /* |
| 20 | * SPI lockdown configuration W25Q64FW. |
| 21 | */ |
| 22 | #define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ |
| 23 | #define SPI_OPTYPE_0 0x01 /* Write, no address */ |
| 24 | |
| 25 | #define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ |
| 26 | #define SPI_OPTYPE_1 0x03 /* Write, address required */ |
| 27 | |
| 28 | #define SPI_OPMENU_2 0x03 /* READ: Read Data */ |
| 29 | #define SPI_OPTYPE_2 0x02 /* Read, address required */ |
| 30 | |
| 31 | #define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ |
| 32 | #define SPI_OPTYPE_3 0x00 /* Read, no address */ |
| 33 | |
| 34 | #define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ |
| 35 | #define SPI_OPTYPE_4 0x03 /* Write, address required */ |
| 36 | |
| 37 | #define SPI_OPMENU_5 0x9f /* RDID: Read ID */ |
| 38 | #define SPI_OPTYPE_5 0x00 /* Read, no address */ |
| 39 | |
| 40 | #define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ |
| 41 | #define SPI_OPTYPE_6 0x03 /* Write, address required */ |
| 42 | |
| 43 | #define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ |
| 44 | #define SPI_OPTYPE_7 0x02 /* Read, address required */ |
| 45 | |
| 46 | #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ |
| 47 | #define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ |
| 48 | (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ |
| 49 | (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ |
| 50 | (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) |
| 51 | #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ |
| 52 | (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) |
| 53 | #define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ |
| 54 | (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) |
| 55 | #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) |
| 56 | |
| 57 | static const struct spi_config spi_config = { |
| 58 | .preop = SPI_OPPREFIX, |
| 59 | .optype = SPI_OPTYPE, |
| 60 | .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, |
| 61 | .lvscc = SPI_VSCC, |
| 62 | .uvscc = SPI_VSCC, |
| 63 | }; |
| 64 | |
| 65 | int mainboard_get_spi_config(struct spi_config *cfg) |
| 66 | { |
| 67 | memcpy(cfg, &spi_config, sizeof(*cfg)); |
| 68 | |
| 69 | return 0; |
| 70 | } |