Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 16 | #include <arch/cache.h> |
| 17 | #include <boot/coreboot_tables.h> |
| 18 | #include <cbmem.h> |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 19 | #include <console/console.h> |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 20 | #include <delay.h> |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 21 | #include <device/device.h> |
| 22 | #include <device/i2c.h> |
Gabe Black | d686acd | 2013-06-30 05:19:53 -0700 | [diff] [blame] | 23 | #include <drivers/parade/ps8625/ps8625.h> |
Gabe Black | c0b2144 | 2013-06-28 14:27:16 -0700 | [diff] [blame] | 24 | #include <ec/google/chromeec/ec.h> |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 25 | #include <edid.h> |
| 26 | #include <soc/tmu.h> |
| 27 | #include <soc/clk.h> |
| 28 | #include <soc/cpu.h> |
| 29 | #include <soc/gpio.h> |
| 30 | #include <soc/power.h> |
| 31 | #include <soc/periph.h> |
| 32 | #include <soc/i2c.h> |
| 33 | #include <soc/dp.h> |
| 34 | #include <soc/fimd.h> |
| 35 | #include <soc/usb.h> |
Gabe Black | d686acd | 2013-06-30 05:19:53 -0700 | [diff] [blame] | 36 | #include <stdlib.h> |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 37 | #include <string.h> |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 38 | #include <symbols.h> |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 39 | #include <vbe.h> |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 40 | |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 41 | /* convenient shorthand (in MB) */ |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 42 | #define DRAM_START ((uintptr_t)_dram/MiB) |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 43 | #define DRAM_SIZE CONFIG_DRAM_SIZE_MB |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 44 | |
| 45 | static struct edid edid = { |
David Hendricks | 7dbf9c6 | 2015-07-30 18:49:48 -0700 | [diff] [blame] | 46 | .mode.ha = 1366, |
| 47 | .mode.va = 768, |
Ronald G. Minnich | 9518b56 | 2013-09-19 16:45:22 -0700 | [diff] [blame] | 48 | .framebuffer_bits_per_pixel = 16, |
Gabe Black | 7b4c432 | 2013-07-25 09:23:00 -0700 | [diff] [blame] | 49 | .x_resolution = 1366, |
| 50 | .y_resolution = 768, |
| 51 | .bytes_per_line = 2 * 1366 |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 52 | }; |
| 53 | |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 54 | /* from the fdt */ |
| 55 | static struct vidinfo vidinfo = { |
| 56 | .vl_freq = 60, |
| 57 | .vl_col = 1366, |
| 58 | .vl_row = 768, |
| 59 | .vl_width = 1366, |
| 60 | .vl_height = 768, |
| 61 | .vl_clkp = 1, |
| 62 | .vl_dp = 1, |
| 63 | .vl_bpix = 4, |
| 64 | .vl_hspw = 32, |
| 65 | .vl_hbpd = 40, |
| 66 | .vl_hfpd = 40, |
| 67 | .vl_vspw = 6, |
| 68 | .vl_vbpd = 10, |
| 69 | .vl_vfpd = 12, |
| 70 | .vl_cmd_allow_len = 0xf, |
| 71 | .win_id = 3, |
| 72 | .dp_enabled = 1, |
| 73 | .dual_lcd_enabled = 0, |
| 74 | .interface_mode = FIMD_RGB_INTERFACE, |
| 75 | }; |
| 76 | |
| 77 | static unsigned char panel_edid[] = { |
| 78 | 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00, |
| 79 | 0x06,0xaf,0x5c,0x31,0x00,0x00,0x00,0x00, |
| 80 | 0x00,0x16,0x01,0x03,0x80,0x1a,0x0e,0x78, |
| 81 | 0x0a,0x99,0x85,0x95,0x55,0x56,0x92,0x28, |
| 82 | 0x22,0x50,0x54,0x00,0x00,0x00,0x01,0x01, |
| 83 | 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, |
| 84 | 0x01,0x01,0x01,0x01,0x01,0x01,0xa3,0x1b, |
| 85 | 0x56,0x7e,0x50,0x00,0x16,0x30,0x30,0x20, |
| 86 | 0x36,0x00,0x00,0x90,0x10,0x00,0x00,0x18, |
| 87 | 0x6d,0x12,0x56,0x7e,0x50,0x00,0x16,0x30, |
| 88 | 0x30,0x20,0x36,0x00,0x00,0x90,0x10,0x00, |
| 89 | 0x00,0x18,0x00,0x00,0x00,0xfe,0x00,0x41, |
| 90 | 0x55,0x4f,0x0a,0x20,0x20,0x20,0x20,0x20, |
| 91 | 0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xfe, |
| 92 | 0x00,0x42,0x31,0x31,0x36,0x58,0x57,0x30, |
| 93 | 0x33,0x20,0x56,0x31,0x20,0x0a,0x00,0x3d, |
| 94 | 0x00,0xc0,0x00,0x00,0x27,0xfd,0x00,0x20, |
| 95 | 0x02,0x59,0x07,0x00,0x64,0x3e,0x07,0x02, |
| 96 | 0x00,0x00,0xcd,0x12,0x59,0xff,0x10,0x03, |
| 97 | 0x00,0x00,0x00,0x00,0x64,0x00,0x00,0x00, |
| 98 | 0x00,0x00,0x00,0x00,0x18,0x00,0x00,0x00, |
| 99 | 0x00,0x00,0x00,0x00,0x05,0x00,0x00,0x00, |
| 100 | 0x9c,0x3f,0x07,0x02,0x31,0xf9,0x00,0x20, |
| 101 | 0x59,0xff,0x10,0x03,0x00,0x00,0x00,0x00, |
| 102 | 0xbc,0x3e,0x07,0x02,0xc0,0x9b,0x01,0x20, |
| 103 | 0x00,0x00,0x00,0x00,0xdb,0xf8,0x00,0x20, |
| 104 | 0x98,0x3e,0x07,0x02,0x8b,0xaf,0x00,0x20, |
| 105 | 0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 106 | 0xe5,0xcd,0x16,0x00,0xe9,0xcd,0x16,0x00, |
| 107 | 0xe8,0x03,0x00,0x00,0x6c,0x55,0x01,0x20, |
| 108 | 0x2c,0x01,0x00,0x00,0x85,0xbb,0x00,0x20, |
| 109 | 0xe8,0x03,0x00,0x00,0xe9,0xcd,0x16,0x00, |
| 110 | }; |
| 111 | |
Ronald G. Minnich | c0872f2 | 2013-07-10 15:22:17 -0700 | [diff] [blame] | 112 | static const struct parade_write parade_writes[] = { |
| 113 | { 0x02, 0xa1, 0x01 }, /* HPD low */ |
| 114 | /* |
| 115 | * SW setting |
| 116 | * [1:0] SW output 1.2V voltage is lower to 96% |
| 117 | */ |
| 118 | { 0x04, 0x14, 0x01 }, |
| 119 | /* |
| 120 | * RCO SS setting |
| 121 | * [5:4] = b01 0.5%, b10 1%, b11 1.5% |
| 122 | */ |
| 123 | { 0x04, 0xe3, 0x20 }, |
| 124 | { 0x04, 0xe2, 0x80 }, /* [7] RCO SS enable */ |
| 125 | /* |
| 126 | * RPHY Setting |
| 127 | * [3:2] CDR tune wait cycle before |
| 128 | * measure for fine tune b00: 1us, |
| 129 | * 01: 0.5us, 10:2us, 11:4us. |
| 130 | */ |
| 131 | { 0x04, 0x8a, 0x0c }, |
| 132 | { 0x04, 0x89, 0x08 }, /* [3] RFD always on */ |
| 133 | /* |
| 134 | * CTN lock in/out: |
| 135 | * 20000ppm/80000ppm. Lock out 2 |
| 136 | * times. |
| 137 | */ |
| 138 | { 0x04, 0x71, 0x2d }, |
| 139 | /* |
| 140 | * 2.7G CDR settings |
| 141 | * NOF=40LSB for HBR CDR setting |
| 142 | */ |
| 143 | { 0x04, 0x7d, 0x07 }, |
| 144 | { 0x04, 0x7b, 0x00 }, /* [1:0] Fmin=+4bands */ |
| 145 | { 0x04, 0x7a, 0xfd }, /* [7:5] DCO_FTRNG=+-40% */ |
| 146 | /* |
| 147 | * 1.62G CDR settings |
| 148 | * [5:2]NOF=64LSB [1:0]DCO scale is 2/5 |
| 149 | */ |
| 150 | { 0x04, 0xc0, 0x12 }, |
| 151 | { 0x04, 0xc1, 0x92 }, /* Gitune=-37% */ |
| 152 | { 0x04, 0xc2, 0x1c }, /* Fbstep=100% */ |
| 153 | { 0x04, 0x32, 0x80 }, /* [7] LOS signal disable */ |
| 154 | /* |
| 155 | * RPIO Setting |
| 156 | * [7:4] LVDS driver bias current : |
| 157 | * 75% (250mV swing) |
| 158 | */ |
| 159 | { 0x04, 0x00, 0xb0 }, |
| 160 | /* |
| 161 | * [7:6] Right-bar GPIO output strength is 8mA |
| 162 | */ |
| 163 | { 0x04, 0x15, 0x40 }, |
| 164 | /* EQ Training State Machine Setting */ |
| 165 | { 0x04, 0x54, 0x10 }, /* RCO calibration start */ |
| 166 | /* [4:0] MAX_LANE_COUNT set to one lane */ |
| 167 | { 0x01, 0x02, 0x81 }, |
| 168 | /* [4:0] LANE_COUNT_SET set to one lane */ |
| 169 | { 0x01, 0x21, 0x81 }, |
| 170 | { 0x00, 0x52, 0x20 }, |
| 171 | { 0x00, 0xf1, 0x03 }, /* HPD CP toggle enable */ |
| 172 | { 0x00, 0x62, 0x41 }, |
| 173 | /* Counter number, add 1ms counter delay */ |
| 174 | { 0x00, 0xf6, 0x01 }, |
| 175 | /* |
| 176 | * [6]PWM function control by |
| 177 | * DPCD0040f[7], default is PWM |
| 178 | * block always works. |
| 179 | */ |
| 180 | { 0x00, 0x77, 0x06 }, |
| 181 | /* |
| 182 | * 04h Adjust VTotal tolerance to |
| 183 | * fix the 30Hz no display issue |
| 184 | */ |
| 185 | { 0x00, 0x4c, 0x04 }, |
| 186 | /* DPCD00400='h00, Parade OUI = 'h001cf8 */ |
| 187 | { 0x01, 0xc0, 0x00 }, |
| 188 | { 0x01, 0xc1, 0x1c }, /* DPCD00401='h1c */ |
| 189 | { 0x01, 0xc2, 0xf8 }, /* DPCD00402='hf8 */ |
| 190 | /* |
| 191 | * DPCD403~408 = ASCII code |
| 192 | * D2SLV5='h4432534c5635 |
| 193 | */ |
| 194 | { 0x01, 0xc3, 0x44 }, |
| 195 | { 0x01, 0xc4, 0x32 }, /* DPCD404 */ |
| 196 | { 0x01, 0xc5, 0x53 }, /* DPCD405 */ |
| 197 | { 0x01, 0xc6, 0x4c }, /* DPCD406 */ |
| 198 | { 0x01, 0xc7, 0x56 }, /* DPCD407 */ |
| 199 | { 0x01, 0xc8, 0x35 }, /* DPCD408 */ |
| 200 | /* |
| 201 | * DPCD40A, Initial Code major revision |
| 202 | * '01' |
| 203 | */ |
| 204 | { 0x01, 0xca, 0x01 }, |
| 205 | /* DPCD40B, Initial Code minor revision '05' */ |
| 206 | { 0x01, 0xcb, 0x05 }, |
Ronald G. Minnich | 0d0b6e2 | 2013-07-10 17:27:45 -0700 | [diff] [blame] | 207 | /* DPCD720, Select external PWM */ |
| 208 | { 0x01, 0xa5, 0x80 }, |
Ronald G. Minnich | c0872f2 | 2013-07-10 15:22:17 -0700 | [diff] [blame] | 209 | /* |
| 210 | * Set LVDS output as 6bit-VESA mapping, |
| 211 | * single LVDS channel |
| 212 | */ |
| 213 | { 0x01, 0xcc, 0x13 }, |
| 214 | /* Enable SSC set by register */ |
| 215 | { 0x02, 0xb1, 0x20 }, |
| 216 | /* |
| 217 | * Set SSC enabled and +/-1% central |
| 218 | * spreading |
| 219 | */ |
| 220 | { 0x04, 0x10, 0x16 }, |
| 221 | /* MPU Clock source: LC => RCO */ |
| 222 | { 0x04, 0x59, 0x60 }, |
| 223 | { 0x04, 0x54, 0x14 }, /* LC -> RCO */ |
| 224 | { 0x02, 0xa1, 0x91 } /* HPD high */ |
| 225 | }; |
| 226 | |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 227 | /* TODO: transplanted DP stuff, clean up once we have something that works */ |
Gabe Black | 63bb610 | 2013-06-19 03:29:45 -0700 | [diff] [blame] | 228 | static enum exynos5_gpio_pin dp_pd_l = GPIO_X35; /* active low */ |
| 229 | static enum exynos5_gpio_pin dp_rst_l = GPIO_Y77; /* active low */ |
| 230 | static enum exynos5_gpio_pin dp_hpd = GPIO_X26; /* active high */ |
| 231 | static enum exynos5_gpio_pin bl_pwm = GPIO_B20; /* active high */ |
| 232 | static enum exynos5_gpio_pin bl_en = GPIO_X22; /* active high */ |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 233 | |
Gabe Black | d686acd | 2013-06-30 05:19:53 -0700 | [diff] [blame] | 234 | static void parade_dp_bridge_setup(void) |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 235 | { |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 236 | int i; |
| 237 | |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 238 | gpio_set_value(dp_pd_l, 1); |
| 239 | gpio_cfg_pin(dp_pd_l, GPIO_OUTPUT); |
| 240 | gpio_set_pull(dp_pd_l, GPIO_PULL_NONE); |
| 241 | |
| 242 | gpio_set_value(dp_rst_l, 0); |
| 243 | gpio_cfg_pin(dp_rst_l, GPIO_OUTPUT); |
| 244 | gpio_set_pull(dp_rst_l, GPIO_PULL_NONE); |
| 245 | udelay(10); |
| 246 | gpio_set_value(dp_rst_l, 1); |
Gabe Black | c0b2144 | 2013-06-28 14:27:16 -0700 | [diff] [blame] | 247 | |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 248 | |
| 249 | gpio_set_pull(dp_hpd, GPIO_PULL_NONE); |
Gabe Black | c0b2144 | 2013-06-28 14:27:16 -0700 | [diff] [blame] | 250 | gpio_cfg_pin(dp_hpd, GPIO_INPUT); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 251 | |
Gabe Black | d686acd | 2013-06-30 05:19:53 -0700 | [diff] [blame] | 252 | /* De-assert PD (and possibly RST) to power up the bridge. */ |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 253 | gpio_set_value(dp_pd_l, 1); |
| 254 | gpio_set_value(dp_rst_l, 1); |
| 255 | |
Gabe Black | d686acd | 2013-06-30 05:19:53 -0700 | [diff] [blame] | 256 | /* Hang around for the bridge to come up. */ |
| 257 | mdelay(40); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 258 | |
Gabe Black | d686acd | 2013-06-30 05:19:53 -0700 | [diff] [blame] | 259 | /* Configure the bridge chip. */ |
| 260 | exynos_pinmux_i2c7(); |
| 261 | i2c_init(7, 100000, 0x00); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 262 | |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 263 | parade_ps8625_bridge_setup(7, 0x48, parade_writes, |
Ronald G. Minnich | c0872f2 | 2013-07-10 15:22:17 -0700 | [diff] [blame] | 264 | ARRAY_SIZE(parade_writes)); |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 265 | /* Spin until the display is ready. |
| 266 | * It's quite important to try really hard to get the display up, |
| 267 | * so be generous. It will typically be ready in only 5 ms. and |
| 268 | * we're out of here. |
| 269 | * If it's not ready after a second, then we're in big trouble. |
| 270 | */ |
| 271 | for(i = 0; i < 1000; i++){ |
| 272 | if (gpio_get_value(dp_hpd)) |
| 273 | break; |
| 274 | mdelay(1); |
| 275 | } |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 276 | } |
| 277 | |
| 278 | /* |
| 279 | * This delay is T3 in the LCD timing spec (defined as >200ms). We set |
| 280 | * this down to 60ms since that's the approximate maximum amount of time |
| 281 | * it'll take a bridge to start outputting LVDS data. The delay of |
| 282 | * >200ms is just a conservative value to avoid turning on the backlight |
| 283 | * when there's random LCD data on the screen. Shaving 140ms off the |
| 284 | * boot is an acceptable trade-off. |
| 285 | */ |
| 286 | #define LCD_T3_DELAY_MS 60 |
| 287 | |
| 288 | #define LCD_T5_DELAY_MS 10 |
| 289 | #define LCD_T6_DELAY_MS 10 |
| 290 | |
| 291 | static void backlight_pwm(void) |
| 292 | { |
| 293 | /*Configure backlight PWM as a simple output high (100% brightness) */ |
Gabe Black | 63bb610 | 2013-06-19 03:29:45 -0700 | [diff] [blame] | 294 | gpio_direction_output(bl_pwm, 1); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 295 | udelay(LCD_T6_DELAY_MS * 1000); |
| 296 | } |
| 297 | |
| 298 | static void backlight_en(void) |
| 299 | { |
| 300 | /* Configure GPIO for LCD_BL_EN */ |
Gabe Black | 63bb610 | 2013-06-19 03:29:45 -0700 | [diff] [blame] | 301 | gpio_direction_output(bl_en, 1); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 302 | } |
| 303 | |
Julius Werner | 79bff70 | 2013-08-15 17:34:45 -0700 | [diff] [blame] | 304 | static enum exynos5_gpio_pin usb_drd0_vbus = GPIO_H00; |
| 305 | static enum exynos5_gpio_pin usb_drd1_vbus = GPIO_H01; |
| 306 | /* static enum exynos5_gpio_pin hsic_reset_l = GPIO_X24; */ |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 307 | |
Julius Werner | 68aef11 | 2013-09-03 15:07:31 -0700 | [diff] [blame] | 308 | static void prepare_usb(void) |
| 309 | { |
| 310 | /* Kick these resets off early so they get at least 100ms to settle */ |
| 311 | reset_usb_drd0_dwc3(); |
| 312 | reset_usb_drd1_dwc3(); |
| 313 | } |
| 314 | |
Julius Werner | 79bff70 | 2013-08-15 17:34:45 -0700 | [diff] [blame] | 315 | static void setup_usb(void) |
| 316 | { |
| 317 | /* HSIC and USB HOST port not needed in firmware on this board */ |
Julius Werner | 68aef11 | 2013-09-03 15:07:31 -0700 | [diff] [blame] | 318 | setup_usb_drd0_phy(); |
| 319 | setup_usb_drd1_phy(); |
| 320 | |
| 321 | setup_usb_drd0_dwc3(); |
| 322 | setup_usb_drd1_dwc3(); |
| 323 | |
Julius Werner | 79bff70 | 2013-08-15 17:34:45 -0700 | [diff] [blame] | 324 | gpio_direction_output(usb_drd0_vbus, 1); |
| 325 | gpio_direction_output(usb_drd1_vbus, 1); |
| 326 | } |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 327 | |
| 328 | static struct edp_video_info dp_video_info = { |
| 329 | .master_mode = 0, |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 330 | .h_sync_polarity = 0, |
| 331 | .v_sync_polarity = 0, |
| 332 | .interlaced = 0, |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 333 | .color_space = COLOR_RGB, |
| 334 | .dynamic_range = VESA, |
| 335 | .ycbcr_coeff = COLOR_YCBCR601, |
| 336 | .color_depth = COLOR_8, |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 337 | }; |
| 338 | |
| 339 | /* FIXME: move some place more appropriate */ |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 340 | #define MAX_DP_TRIES 5 |
| 341 | |
Julius Werner | ad4556f2 | 2013-08-21 17:33:31 -0700 | [diff] [blame] | 342 | static void setup_storage(void) |
| 343 | { |
| 344 | /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ |
| 345 | if (clock_set_dwmci(PERIPH_ID_SDMMC0)) |
| 346 | printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__); |
| 347 | exynos_pinmux_sdmmc0(); |
| 348 | |
| 349 | /* MMC2: Removable, 4 bit mode, no GPIO. */ |
| 350 | /* (Must be after romstage to avoid breaking SDMMC boot.) */ |
| 351 | clock_set_dwmci(PERIPH_ID_SDMMC2); |
| 352 | exynos_pinmux_sdmmc2(); |
| 353 | } |
| 354 | |
Gabe Black | 04d6e01 | 2013-06-23 03:16:46 -0700 | [diff] [blame] | 355 | static void gpio_init(void) |
| 356 | { |
| 357 | /* Set up the I2C busses. */ |
| 358 | exynos_pinmux_i2c2(); |
| 359 | exynos_pinmux_i2c4(); |
| 360 | exynos_pinmux_i2c7(); |
| 361 | exynos_pinmux_i2c8(); |
| 362 | exynos_pinmux_i2c9(); |
| 363 | exynos_pinmux_i2c10(); |
| 364 | } |
| 365 | |
Gabe Black | c0b2144 | 2013-06-28 14:27:16 -0700 | [diff] [blame] | 366 | enum { |
| 367 | FET_CTRL_WAIT = 3 << 2, |
| 368 | FET_CTRL_ADENFET = 1 << 1, |
| 369 | FET_CTRL_ENFET = 1 << 0 |
| 370 | }; |
| 371 | |
| 372 | static void tps65090_thru_ec_fet_set(int index) |
| 373 | { |
| 374 | uint8_t value = FET_CTRL_ADENFET | FET_CTRL_WAIT | FET_CTRL_ENFET; |
| 375 | |
| 376 | if (google_chromeec_i2c_xfer(0x48, 0xe + index, 1, &value, 1, 0)) { |
| 377 | printk(BIOS_ERR, |
| 378 | "Error sending i2c pass through command to EC.\n"); |
| 379 | return; |
| 380 | } |
| 381 | } |
| 382 | |
| 383 | static void lcd_vdd(void) |
| 384 | { |
| 385 | /* Enable FET6, lcd panel */ |
| 386 | tps65090_thru_ec_fet_set(6); |
| 387 | } |
| 388 | |
| 389 | static void backlight_vdd(void) |
| 390 | { |
| 391 | /* Enable FET1, backlight */ |
| 392 | tps65090_thru_ec_fet_set(1); |
| 393 | } |
| 394 | |
Julius Werner | ad4556f2 | 2013-08-21 17:33:31 -0700 | [diff] [blame] | 395 | static void sdmmc_vdd(void) |
| 396 | { |
| 397 | /* Enable FET4, P3.3V_SDCARD */ |
| 398 | tps65090_thru_ec_fet_set(4); |
| 399 | } |
| 400 | |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 401 | /* this happens after cpu_init where exynos resources are set */ |
| 402 | static void mainboard_init(device_t dev) |
| 403 | { |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 404 | /* we'll stick with the crummy u-boot struct for now.*/ |
| 405 | /* doing this as an auto since the struct has to be writeable */ |
| 406 | struct edp_device_info device_info; |
| 407 | |
Stefan Reinauer | 80e6293 | 2013-07-29 15:52:23 -0700 | [diff] [blame] | 408 | void *fb_addr = (void *)(get_fb_base_kb() * KiB); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 409 | |
Julius Werner | 68aef11 | 2013-09-03 15:07:31 -0700 | [diff] [blame] | 410 | prepare_usb(); |
Gabe Black | 04d6e01 | 2013-06-23 03:16:46 -0700 | [diff] [blame] | 411 | gpio_init(); |
Julius Werner | ad4556f2 | 2013-08-21 17:33:31 -0700 | [diff] [blame] | 412 | setup_storage(); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 413 | tmu_init(&exynos5420_tmu_info); |
| 414 | |
| 415 | /* Clock Gating all the unused IP's to save power */ |
| 416 | clock_gate(); |
| 417 | |
Julius Werner | ad4556f2 | 2013-08-21 17:33:31 -0700 | [diff] [blame] | 418 | sdmmc_vdd(); |
| 419 | |
Stefan Reinauer | f175191 | 2013-05-20 15:17:44 -0700 | [diff] [blame] | 420 | set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 421 | |
Ronald G. Minnich | 88750cb | 2013-07-16 17:30:16 -0700 | [diff] [blame] | 422 | /* |
| 423 | * The reset value for FIMD SYSMMU register MMU_CTRL:0x14640000 |
| 424 | * should be 0 according to the datasheet, but has experimentally |
| 425 | * been found to come up as 3. This means FIMD SYSMMU is on by |
| 426 | * default on Exynos5420. For now we are disabling FIMD SYSMMU. |
| 427 | */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 428 | write32((void *)0x14640000, 0x0); |
| 429 | write32((void *)0x14680000, 0x0); |
Ronald G. Minnich | 88750cb | 2013-07-16 17:30:16 -0700 | [diff] [blame] | 430 | |
Gabe Black | c0b2144 | 2013-06-28 14:27:16 -0700 | [diff] [blame] | 431 | lcd_vdd(); |
Stefan Reinauer | c2c4f84 | 2013-05-20 12:51:02 -0700 | [diff] [blame] | 432 | |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 433 | /* Start the fimd running before you do the phy and lcd setup. |
| 434 | * why do fimd before training etc? |
| 435 | * because we need a data stream from |
| 436 | * the fimd or the clock recovery step fails. |
| 437 | */ |
| 438 | vidinfo.screen_base = fb_addr; |
| 439 | exynos_fimd_lcd_init(&vidinfo); |
| 440 | |
Gabe Black | d686acd | 2013-06-30 05:19:53 -0700 | [diff] [blame] | 441 | parade_dp_bridge_setup(); |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 442 | |
| 443 | /* this might get more dynamic in future ... */ |
| 444 | memset(&device_info, 0, sizeof(device_info)); |
Gabe Black | 04bfbf5 | 2014-01-22 20:50:27 -0800 | [diff] [blame] | 445 | device_info.disp_info.name = (char *)"Peach Pit display"; |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 446 | device_info.disp_info.h_total = 1366; |
| 447 | device_info.disp_info.v_total = 768; |
| 448 | device_info.video_info = dp_video_info; |
| 449 | device_info.raw_edid = panel_edid; |
| 450 | exynos_init_dp(&device_info); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 451 | |
Gabe Black | d686acd | 2013-06-30 05:19:53 -0700 | [diff] [blame] | 452 | backlight_vdd(); |
| 453 | backlight_pwm(); |
| 454 | backlight_en(); |
Julius Werner | 68aef11 | 2013-09-03 15:07:31 -0700 | [diff] [blame] | 455 | |
| 456 | setup_usb(); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 457 | } |
| 458 | |
| 459 | static void mainboard_enable(device_t dev) |
| 460 | { |
| 461 | dev->ops->init = &mainboard_init; |
| 462 | |
Gabe Black | ee4bfbf | 2013-08-13 21:05:43 -0700 | [diff] [blame] | 463 | /* set up caching for the DRAM */ |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 464 | mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 465 | mmu_config_range((uintptr_t)_dma_coherent/MiB, |
| 466 | _dma_coherent_size/MiB, DCACHE_OFF); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 467 | |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 468 | const unsigned epll_hz = 192000000; |
| 469 | const unsigned sample_rate = 48000; |
| 470 | const unsigned lr_frame_size = 256; |
| 471 | clock_epll_set_rate(epll_hz); |
| 472 | clock_select_i2s_clk_source(); |
| 473 | clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size); |
| 474 | |
| 475 | power_enable_xclkout(); |
| 476 | } |
| 477 | |
| 478 | struct chip_operations mainboard_ops = { |
David Hendricks | 054c83a | 2015-01-09 11:46:43 -0800 | [diff] [blame] | 479 | .name = "peach_pit", |
| 480 | .enable_dev = mainboard_enable, |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 481 | }; |
Julius Werner | b8fad3d | 2013-08-27 15:48:32 -0700 | [diff] [blame] | 482 | |
| 483 | void lb_board(struct lb_header *header) |
| 484 | { |
| 485 | struct lb_range *dma; |
| 486 | |
| 487 | dma = (struct lb_range *)lb_new_record(header); |
| 488 | dma->tag = LB_TAB_DMA; |
| 489 | dma->size = sizeof(*dma); |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 490 | dma->range_start = (uintptr_t)_dma_coherent; |
| 491 | dma->range_size = _dma_coherent_size; |
Julius Werner | b8fad3d | 2013-08-27 15:48:32 -0700 | [diff] [blame] | 492 | } |