Patrick Georgi | 04746fc | 2015-06-05 18:53:43 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Patrick Georgi | 04746fc | 2015-06-05 18:53:43 +0200 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <string.h> |
| 17 | #include <arch/io.h> |
| 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <console/console.h> |
| 21 | #include <vendorcode/google/chromeos/chromeos.h> |
| 22 | #include <ec/google/chromeec/ec.h> |
| 23 | #include <soc/gpio.h> |
| 24 | #include <soc/sata.h> |
| 25 | |
| 26 | #define GPIO_SPI_WP 58 |
| 27 | #define GPIO_REC_MODE 12 |
| 28 | |
| 29 | #define FLAG_SPI_WP 0 |
| 30 | #define FLAG_REC_MODE 1 |
| 31 | #define FLAG_DEV_MODE 2 |
| 32 | |
| 33 | #ifndef __PRE_RAM__ |
| 34 | #include <boot/coreboot_tables.h> |
| 35 | |
| 36 | #define GPIO_COUNT 6 |
| 37 | |
Patrick Georgi | 04746fc | 2015-06-05 18:53:43 +0200 | [diff] [blame] | 38 | void fill_lb_gpios(struct lb_gpios *gpios) |
| 39 | { |
| 40 | struct lb_gpio *gpio; |
| 41 | |
| 42 | gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); |
| 43 | gpios->count = GPIO_COUNT; |
| 44 | |
| 45 | gpio = gpios->gpios; |
Patrick Georgi | ea31f63 | 2015-06-30 12:40:43 +0200 | [diff] [blame] | 46 | fill_lb_gpio(gpio++, GPIO_SPI_WP, ACTIVE_HIGH, "write protect", |
| 47 | get_gpio(GPIO_SPI_WP)); |
Patrick Georgi | 04746fc | 2015-06-05 18:53:43 +0200 | [diff] [blame] | 48 | fill_lb_gpio(gpio++, GPIO_REC_MODE, ACTIVE_LOW, "recovery", |
| 49 | get_recovery_mode_switch()); |
| 50 | fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", |
| 51 | get_developer_mode_switch()); |
| 52 | fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); |
| 53 | fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); |
Patrick Georgi | ea31f63 | 2015-06-30 12:40:43 +0200 | [diff] [blame] | 54 | fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); |
Patrick Georgi | 04746fc | 2015-06-05 18:53:43 +0200 | [diff] [blame] | 55 | } |
| 56 | #endif |
| 57 | |
| 58 | int get_write_protect_state(void) |
| 59 | { |
| 60 | device_t dev; |
| 61 | #ifdef __PRE_RAM__ |
| 62 | dev = PCI_DEV(0, 0x1f, 2); |
| 63 | #else |
| 64 | dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); |
| 65 | #endif |
| 66 | return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; |
| 67 | } |
| 68 | |
| 69 | int get_developer_mode_switch(void) |
| 70 | { |
| 71 | return 0; |
| 72 | } |
| 73 | |
| 74 | int get_recovery_mode_switch(void) |
| 75 | { |
| 76 | device_t dev; |
| 77 | #ifdef __PRE_RAM__ |
| 78 | dev = PCI_DEV(0, 0x1f, 2); |
| 79 | #else |
| 80 | dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); |
| 81 | #endif |
| 82 | return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; |
| 83 | } |
| 84 | |
| 85 | #ifdef __PRE_RAM__ |
| 86 | void save_chromeos_gpios(void) |
| 87 | { |
| 88 | u32 flags = 0; |
| 89 | |
| 90 | /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ |
| 91 | if (get_gpio(GPIO_SPI_WP)) |
| 92 | flags |= (1 << FLAG_SPI_WP); |
| 93 | |
| 94 | /* Recovery: GPIO12 = RECOVERY_L, active low */ |
| 95 | if (!get_gpio(GPIO_REC_MODE)) |
| 96 | flags |= (1 << FLAG_REC_MODE); |
| 97 | |
| 98 | /* Developer: Virtual */ |
| 99 | |
| 100 | pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); |
| 101 | } |
| 102 | #endif |