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review.coreboot.org / coreboot / 9631016660423d0585a1 / . / src / mainboard / google / cyan / gpio.c
blob: 66c7c2a84f100f8a3a86924b629b3b3b0f0834b3 [file] [log] [blame]
Lee Leahy89b5fbd2015-05-11 17:24:31 -0700[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright(C) 2013 Google Inc.
5 * Copyright (C) 2015 Intel Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahy89b5fbd2015-05-11 17:24:31 -0700[diff] [blame]15 */
16
17#include "irqroute.h"
18#include <soc/gpio.h>
19#include <stdlib.h>
20#include "gpio.h"
21
22/* South East Community */
23static const struct soc_gpio_map gpse_gpio_map[] = {
24 Native_M1,/* MF_PLT_CLK0 */
25 GPIO_NC, /* 01 PWM1 */
26 GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */
27 GPIO_NC, /* 03 MF_PLT_CLK4 */
28 GPIO_NC, /* 04 MF_PLT_CLK3 */
29 GPIO_NC, /* PWM0 05 */
30 GPIO_NC, /* 06 MF_PLT_CLK5 */
31 GPIO_NC, /* 07 MF_PLT_CLK2 */
32 GPIO_NC, /* 15 SDMMC2_D3_CD_B */
33 Native_M1, /* 16 SDMMC1_CLK */
34 NATIVE_PU20K(1), /* 17 SDMMC1_D0 */
35 GPIO_NC, /* 18 SDMMC2_D1 */
36 GPIO_NC, /* 19 SDMMC2_CLK */
37 NATIVE_PU20K(1),/* 20 SDMMC1_D2 */
38 GPIO_NC, /* 21 SDMMC2_D2 */
39 GPIO_NC, /* 22 SDMMC2_CMD */
40 NATIVE_PU20K(1), /* 23 SDMMC1_CMD */
41 NATIVE_PU20K(1), /* 24 SDMMC1_D1 */
42 GPIO_NC, /* 25 SDMMC2_D0 */
43 NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */
44 NATIVE_PU20K(1), /* 30 SDMMC3_D1 */
45 Native_M1, /* 31 SDMMC3_CLK */
46 NATIVE_PU20K(1), /* 32 SDMMC3_D3 */
47 NATIVE_PU20K(1), /* 33 SDMMC3_D2 */
48 NATIVE_PU20K(1), /* 34 SDMMC3_CMD */
49 NATIVE_PU20K(1), /* 35 SDMMC3_D0 */
50 NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */
51 Native_M1, /* 46 LPC_CLKRUNB */
52 NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */
53 Native_M1, /* 48 LPC_FRAMEB */
54 Native_M1, /* 49 MF_LPC_CLKOUT1 */
55 NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */
56 Native_M1, /* 51 MF_LPC_CLKOUT0 */
57 NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */
58 Native_M1,/* SPI1_MISO */
59 Native_M1, /* 61 SPI1_CS0_B */
60 Native_M1, /* SPI1_CLK */
61 NATIVE_PU20K(1), /* 63 MMC1_D6 */
62 Native_M1, /* 62 SPI1_MOSI */
63 NATIVE_PU20K(1), /* 65 MMC1_D5 */
64 GPIO_NC, /* SPI1_CS1_B 66 */
65 NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */
66 NATIVE_PU20K(1), /* 68 MMC1_D7 */
67 GPIO_NC, /* 69 MMC1_RCLK */
68 Native_M1, /* 75 GPO USB_OC1_B */
69 Native_M1, /* 76 PMU_RESETBUTTON_B */
70 GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
71 /* GPIO_ALERT 77 */
72 Native_M1, /* 78 SDMMC3_PWR_EN_B */
73 GPIO_NC, /* 79 GPI ILB_SERIRQ */
74 Native_M1, /* 80 USB_OC0_B */
75 NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */
76 GPIO_NC, /* 82 spkr asummed gpio number */
77 Native_M1, /* 83 SUSPWRDNACK */
78 SPARE_PIN,/* 84 spare pin */
79 Native_M1, /* 85 SDMMC3_1P8_EN */
80 GPIO_END
81};
82
83
84/* South West Community */
85static const struct soc_gpio_map gpsw_gpio_map[] = {
86 GPIO_NC, /* 00 FST_SPI_D2 */
87 Native_M1, /* 01 FST_SPI_D0 */
88 Native_M1, /* 02 FST_SPI_CLK */
89 GPIO_NC, /* 03 FST_SPI_D3 */
90 GPIO_NC, /* GPO FST_SPI_CS1_B */
91 Native_M1, /* 05 FST_SPI_D1 */
92 Native_M1, /* 06 FST_SPI_CS0_B */
Jagadish Krishnamoorthy367ddc92015-06-23 19:23:25 -0700[diff] [blame]93 GPIO_NC, /* 07 FST_SPI_CS2_B */
Lee Leahy89b5fbd2015-05-11 17:24:31 -0700[diff] [blame]94 GPIO_NC, /* 15 UART1_RTS_B */
95 Native_M2, /* 16 UART1_RXD */
96 GPIO_NC, /* 17 UART2_RXD */
97 GPIO_NC, /* 18 UART1_CTS_B */
98 GPIO_NC, /* 19 UART2_RTS_B */
99 Native_M2, /* 20 UART1_TXD */
100 GPIO_NC, /* 21 UART2_TXD */
101 GPIO_NC, /* 22 UART2_CTS_B */
102 GPIO_NC, /* 30 MF_HDA_CLK */
103 GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */
104 GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */
105 GPIO_NC, /* 33 MF_HDA_SDO */
106 GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA),
107 /* 34 MF_HDA_DOCKRSTB */
108 GPIO_NC, /* 35 MF_HDA_SYNC */
109 GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */
110 GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA),
111 /* 37 MF_HDA_DOCKENB */
112 NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */
113 GPIO_NC, /* 46 I2C4_SDA */
114 NATIVE_PU20K(2), /* 47 I2C6_SDA */
115 NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */
116 GPIO_NC, /* 49 I2C_NFC_SDA */
117 GPIO_NC, /* 50 I2C4_SCL */
118 NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */
119 GPIO_NC, /* 52 I2C_NFC_SCL */
120 NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */
121 NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */
122 NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */
123 NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */
124 GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/
125 NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */
126 NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */
127 GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */
128 GPIO_OUT_HIGH, /* 75 SATA_GP0 */
129 GPIO_NC, /* 76 GPI SATA_GP1 */
Hannah Williamsb61ed352015-07-18 16:04:21 -0700[diff] [blame]130 GPIO_INPUT_PU_20K, /* 77 SATA_LEDN, EC_IN_RW */
Lee Leahy89b5fbd2015-05-11 17:24:31 -0700[diff] [blame]131 GPIO_NC, /* 78 HSIC AUX1 / SV Mode/ SATA_GP2 */
132 Native_M1, /* 79 MF_SMB_ALERTB */
133 GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
134 Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
135 Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
136 /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
137 Native_M1, /* 90 PCIE_CLKREQ0B */
138 GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */
139 Native_M1, /* 92 GP_SSP_2_CLK */
140 NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
141 Native_M1, /* 94 GP_SSP_2_RXD */
142 GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),
143 /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */
144 Native_M1, /* 96 GP_SSP_2_FS */
145 NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */
146 GPIO_END
147};
148
149
150/* North Community */
151static const struct soc_gpio_map gpn_gpio_map[] = {
152 Native_M5, /* 00 GPIO_DFX0 */
153 Native_M5, /* 01 GPIO_DFX3 */
154 Native_M1, /* 02 GPIO_DFX7 */
155 Native_M5, /* 03 GPIO_DFX1 */
156 Native_M1, /* 04 GPIO_DFX5 */
157 Native_M1, /* 05 GPIO_DFX4 */
158 GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA),
159 /* 06 GPIO_DFX8 */
160 Native_M5, /* 07 GPIO_DFX2 */
161 Native_M8, /* 08 GPIO_DFX6 */
162 GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
163 UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
164 GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
165 GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
166 /* 17 GPIO_SUS3 */
167 GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
168 /* 18 GPIO_SUS7 */
169 GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
170 /* 19 GPIO_SUS1 */
171 GPIO_NC, /* 20 GPIO_SUS5 */
172 GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA),
173 /* 21 SEC_GPIO_SUS11 */
174 GPIO_NC, /* 22 GPIO_SUS4 */
175 GPIO_NC,
176 /* 23 SEC_GPIO_SUS8 */
177 Native_M6, /* 24 GPIO_SUS2 */
178 GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */
179 Native_M1, /* 26 CX_PREQ_B */
180 GPO_FUNC(0, 0), /* 27 SEC_GPIO_SUS9 */
181 Native_M1, /* 30 TRST_B */
182 Native_M1, /* 31 TCK */
183 GPIO_SKIP, /* 32 PROCHOT_B */
184 GPIO_SKIP, /* 33 SVID0_DATA */
185 Native_M1, /* 34 TMS */
186 GPIO_NC, /* 35 CX_PRDY_B_2 */
187 GPIO_NC, /* 36 TDO_2 */
188 Native_M1, /* 37 CX_PRDY_B */
189 GPIO_SKIP, /* 38 SVID0_ALERT_B */
190 Native_M1, /* 39 TDO */
191 GPIO_SKIP, /* 40 SVID0_CLK */
192 Native_M1, /* 41 TDI */
193 Native_M2, /* 45 GP_CAMERASB05 */
194 Native_M2, /* 46 GP_CAMERASB02 */
195 Native_M2, /* 47 GP_CAMERASB08 */
196 Native_M2, /* 48 GP_CAMERASB00 */
197 Native_M2, /* 49 GP_CAMERASBO6 */
198 GPIO_NC, /* 50 GP_CAMERASB10 */
199 Native_M2, /* 51 GP_CAMERASB03 */
200 GPIO_NC, /* 52 GP_CAMERASB09 */
201 Native_M2, /* 53 GP_CAMERASB01 */
202 Native_M2, /* 54 GP_CAMERASB07 */
203 GPIO_NC, /* 55 GP_CAMERASB11 */
204 Native_M2, /* 56 GP_CAMERASB04 */
205 GPIO_NC, /* 60 PANEL0_BKLTEN */
206 GPIO_NC, /* 61 HV_DDI0_HPD */
207 NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */
208 Native_M1, /* 63 PANEL1_BKLTCTL */
209 NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */
210 GPIO_NC, /* 65 PANEL0_BKLTCTL */
211 GPIO_NC, /* 66 HV_DDI0_DDC_SDA */
212 NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */
213 NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */
214 Native_M1, /* 69 PANEL1_VDDEN */
215 Native_M1, /* 70 PANEL1_BKLTEN */
216 GPIO_NC, /* 71 HV_DDI0_DDC_SCL */
217 GPIO_NC, /* 72 PANEL0_VDDEN */
218 GPIO_END
219};
220
221
222/* East Community */
223static const struct soc_gpio_map gpe_gpio_map[] = {
224 Native_M1, /* 00 PMU_SLP_S3_B */
225 GPIO_NC, /* 01 PMU_BATLOW_B */
226 Native_M1, /* 02 SUS_STAT_B */
227 Native_M1, /* 03 PMU_SLP_S0IX_B */
228 Native_M1, /* 04 PMU_AC_PRESENT */
229 Native_M1, /* 05 PMU_PLTRST_B */
230 Native_M1, /* 06 PMU_SUSCLK */
231 GPIO_NC, /* 07 PMU_SLP_LAN_B */
232 Native_M1, /* 08 PMU_PWRBTN_B */
233 Native_M1, /* 09 PMU_SLP_S4_B */
234 NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */
235 GPIO_NC, /* 11 PMU_WAKE_LAN_B */
236 GPIO_NC, /* 15 MF_GPIO_3 */
237 GPIO_NC, /* 16 MF_GPIO_7 */
238 GPIO_NC, /* 17 MF_I2C1_SCL */
239 GPIO_NC, /* 18 MF_GPIO_1 */
240 GPIO_NC, /* 19 MF_GPIO_5 */
241 GPIO_NC, /* 20 MF_GPIO_9 */
242 GPIO_NC, /* 21 MF_GPIO_0 */
243 GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */
244 GPIO_NC, /* 23 MF_GPIO_8 */
245 GPIO_NC, /* 24 MF_GPIO_2 */
246 GPIO_NC, /* 25 MF_GPIO_6 */
247 GPIO_NC, /* 26 MF_I2C1_SDA */
248 GPIO_END
249};
250
251
252static struct soc_gpio_config gpio_config = {
253 /* BSW */
254 /* gpio configuration for EVT board */
255 .north = gpn_gpio_map,
256 .southeast = gpse_gpio_map,
257 .southwest = gpsw_gpio_map,
258 .east = gpe_gpio_map
259};
260
261struct soc_gpio_config *mainboard_get_gpios(void)
262{
263 return get_override_gpios(&gpio_config);
264}
265
266__attribute__((weak)) struct soc_gpio_config *get_override_gpios(
267 struct soc_gpio_config *config)
268{
269 return config;
270}