Duncan Laurie | 09170f1 | 2015-10-09 09:25:32 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2015 Google Inc. |
| 6 | * Copyright (C) 2015 Intel Corporation |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Duncan Laurie | 09170f1 | 2015-10-09 09:25:32 -0700 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | DefinitionBlock( |
| 19 | "dsdt.aml", |
| 20 | "DSDT", |
| 21 | 0x05, // DSDT revision: ACPI v5.0 |
| 22 | "COREv4", // OEM id |
| 23 | "COREBOOT", // OEM table id |
| 24 | 0x20110725 // OEM revision |
| 25 | ) |
| 26 | { |
| 27 | // Some generic macros |
| 28 | #include <soc/intel/skylake/acpi/platform.asl> |
| 29 | |
| 30 | // global NVS and variables |
| 31 | #include <soc/intel/skylake/acpi/globalnvs.asl> |
| 32 | |
| 33 | // CPU |
| 34 | #include <soc/intel/skylake/acpi/cpu.asl> |
| 35 | |
| 36 | Scope (\_SB) { |
| 37 | Device (PCI0) |
| 38 | { |
| 39 | #include <soc/intel/skylake/acpi/systemagent.asl> |
| 40 | #include <soc/intel/skylake/acpi/pch.asl> |
| 41 | } |
| 42 | |
| 43 | // Dynamic Platform Thermal Framework |
| 44 | #include "acpi/dptf.asl" |
| 45 | } |
| 46 | |
| 47 | // Chrome OS specific |
| 48 | #include "acpi/chromeos.asl" |
| 49 | #include <vendorcode/google/chromeos/acpi/chromeos.asl> |
| 50 | |
| 51 | // Chipset specific sleep states |
| 52 | #include <soc/intel/skylake/acpi/sleepstates.asl> |
| 53 | |
| 54 | // Mainboard specific |
| 55 | #include "acpi/mainboard.asl" |
| 56 | } |