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review.coreboot.org / coreboot / 9631016660423d0585a1 / . / src / mainboard / gizmosphere / gizmo2 / buildOpts.c
blob: 8162d428a88208b58b111bc4ef588266d4d0fc04 [file] [log] [blame]
Dave Frodinc43bce52014-12-03 08:22:46 -0700[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Dave Frodinc43bce52014-12-03 08:22:46 -0700[diff] [blame]14 */
15
16/**
17 * @file
18 *
19 * AMD User options selection for a Brazos platform solution system
20 *
21 * This file is placed in the user's platform directory and contains the
22 * build option selections desired for that platform.
23 *
24 * For Information about this file, see @ref platforminstall.
25 *
Dave Frodinc43bce52014-12-03 08:22:46 -0700[diff] [blame]26 */
27
28#include <stdlib.h>
29#include "AGESA.h"
30//#include "CommonReturns.h"
31#include "Filecode.h"
32#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
33
34#define INSTALL_FT3_SOCKET_SUPPORT TRUE
35#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
36
37#define INSTALL_G34_SOCKET_SUPPORT FALSE
38#define INSTALL_C32_SOCKET_SUPPORT FALSE
39#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
40#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
41#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
42#define INSTALL_FS1_SOCKET_SUPPORT FALSE
43#define INSTALL_FM1_SOCKET_SUPPORT FALSE
44#define INSTALL_FP2_SOCKET_SUPPORT FALSE
45#define INSTALL_FT1_SOCKET_SUPPORT FALSE
46#define INSTALL_AM3_SOCKET_SUPPORT FALSE
47#define INSTALL_FM2_SOCKET_SUPPORT FALSE
48
49
50#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT
51 #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE
52 #undef INSTALL_FT3_SOCKET_SUPPORT
53 #define INSTALL_FT3_SOCKET_SUPPORT FALSE
54 #endif
55#endif
56
57//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
58//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
59#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
60//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
61//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
62//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
63#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
64#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
65#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
66//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
67#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
68//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
69#define BLDOPT_REMOVE_SRAT FALSE //TRUE
70#define BLDOPT_REMOVE_SLIT FALSE //TRUE
71#define BLDOPT_REMOVE_WHEA FALSE //TRUE
72#define BLDOPT_REMOVE_CRAT TRUE
73#define BLDOPT_REMOVE_CDIT TRUE
74#define BLDOPT_REMOVE_DMI TRUE
75//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
76//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
77//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
78//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
79//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
80//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
81
82//This element selects whether P-States should be forced to be independent,
83// as reported by the ACPI _PSD object. For single-link processors,
84// setting TRUE for OS to support this feature.
85
86//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
87
88#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
89#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
90/* Build configuration values here.
91 */
92#define BLDCFG_VRM_CURRENT_LIMIT 15000
93#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000
94#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000
95#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
96#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000
97#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
98#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
99#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0
100#define BLDCFG_VRM_SLEW_RATE 10000
101#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE
102#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
103
104#define BLDCFG_PLAT_NUM_IO_APICS 3
105#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000
106#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
107#define BLDCFG_MEM_INIT_PSTATE 0
108#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the
109 // core for C-state entry requests. A value
110 // of 0 in this field specifies that the core
111 // does not trap any IO addresses for C-state entry.
112 // Values greater than 0xFFF8 results in undefined behavior.
113#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
114
115#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
116
117#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
118#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
119#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
120#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
121#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
122#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
123#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
124#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
125#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
126#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
127#define BLDCFG_MEMORY_POWER_DOWN TRUE
128#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
129#define BLDCFG_ONLINE_SPARE FALSE
130#define BLDCFG_BANK_SWIZZLE TRUE
131#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
132#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
133#define BLDCFG_DQS_TRAINING_CONTROL TRUE
134#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
135#define BLDCFG_USE_BURST_MODE FALSE
136#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
137#define BLDCFG_ENABLE_ECC_FEATURE TRUE
138#define BLDCFG_ECC_REDIRECTION FALSE
139#define BLDCFG_SCRUB_DRAM_RATE 0
140#define BLDCFG_SCRUB_L2_RATE 0
141#define BLDCFG_SCRUB_L3_RATE 0
142#define BLDCFG_SCRUB_IC_RATE 0
143#define BLDCFG_SCRUB_DC_RATE 0
144#define BLDCFG_ECC_SYNC_FLOOD TRUE
145#define BLDCFG_ECC_SYMBOL_SIZE 4
146#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul
147#define BLDCFG_1GB_ALIGN FALSE
148#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
149#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
150#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled
151#define BLDCFG_IOMMU_SUPPORT FALSE
152#define OPTION_GFX_INIT_SVIEW FALSE
153//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife
154
155//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL
156#define BLDCFG_CFG_ABM_SUPPORT TRUE
157
158#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
159//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
160//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
161//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
162
163#ifdef PCIEX_BASE_ADDRESS
164#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS
165#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20)
166#endif
167
168#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
169#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
170#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed
171
172/* Process the options...
173 * This file include MUST occur AFTER the user option selection settings
174 */
175#define AGESA_ENTRY_INIT_RESET TRUE
176#define AGESA_ENTRY_INIT_RECOVERY FALSE
177#define AGESA_ENTRY_INIT_EARLY TRUE
178#define AGESA_ENTRY_INIT_POST TRUE
179#define AGESA_ENTRY_INIT_ENV TRUE
180#define AGESA_ENTRY_INIT_MID TRUE
181#define AGESA_ENTRY_INIT_LATE TRUE
182#define AGESA_ENTRY_INIT_S3SAVE TRUE
183#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
184#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
185#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
186/*
187 * Customized OEM build configurations for FCH component
188 */
189// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
190// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
191// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
192// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
193// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
194// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
195// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
196// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
197// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
198// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
199// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
200// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
201// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
202// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
203// #define BLDCFG_AZALIA_SSID 0x780D1022
204// #define BLDCFG_SMBUS_SSID 0x780B1022
205// #define BLDCFG_IDE_SSID 0x780C1022
206// #define BLDCFG_SATA_AHCI_SSID 0x78011022
207// #define BLDCFG_SATA_IDE_SSID 0x78001022
208// #define BLDCFG_SATA_RAID5_SSID 0x78031022
209// #define BLDCFG_SATA_RAID_SSID 0x78021022
210// #define BLDCFG_EHCI_SSID 0x78081022
211// #define BLDCFG_OHCI_SSID 0x78071022
212// #define BLDCFG_LPC_SSID 0x780E1022
213// #define BLDCFG_SD_SSID 0x78061022
214// #define BLDCFG_XHCI_SSID 0x78121022
215// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
216// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
217// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
218// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
219// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
220// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
221// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
222// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
223// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
224// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
225// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
226
227CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
228{
229 { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
230 { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
231 { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
232 { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
233 { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
234 { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
235 { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
236 { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
237 { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
238 { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
239 { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
240 { CPU_LIST_TERMINAL }
241};
242
243#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList
244
245//#include "KeralaInstall.h"
246
247/* Include the files that instantiate the configuration definitions. */
248#include "cpuRegisters.h"
249#include "cpuFamRegisters.h"
250#include "cpuFamilyTranslation.h"
251#include "AdvancedApi.h"
252#include "heapManager.h"
253#include "CreateStruct.h"
254#include "cpuFeatures.h"
255#include "Table.h"
256#include "CommonReturns.h"
257#include "cpuEarlyInit.h"
258#include "cpuLateInit.h"
259#include "GnbInterface.h"
260
261 // This is the delivery package title, "BrazosPI"
262 // This string MUST be exactly 8 characters long
263#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
264
265 // This is the release version number of the AGESA component
266 // This string MUST be exactly 12 characters long
267#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
268
269/* MEMORY_BUS_SPEED */
270//#define DDR400_FREQUENCY 200 ///< DDR 400
271//#define DDR533_FREQUENCY 266 ///< DDR 533
272//#define DDR667_FREQUENCY 333 ///< DDR 667
273//#define DDR800_FREQUENCY 400 ///< DDR 800
274//#define DDR1066_FREQUENCY 533 ///< DDR 1066
275//#define DDR1333_FREQUENCY 667 ///< DDR 1333
276//#define DDR1600_FREQUENCY 800 ///< DDR 1600
277//#define DDR1866_FREQUENCY 933 ///< DDR 1866
278//#define DDR2100_FREQUENCY 1050 ///< DDR 2100
279//#define DDR2133_FREQUENCY 1066 ///< DDR 2133
280//#define DDR2400_FREQUENCY 1200 ///< DDR 2400
281//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
282//
283///* QUANDRANK_TYPE*/
284//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
285//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
286//
287///* USER_MEMORY_TIMING_MODE */
288//#define TIMING_MODE_AUTO 0 ///< Use best rate possible
289//#define TIMING_MODE_LIMITED 1 ///< Set user top limit
290//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
291//
292///* POWER_DOWN_MODE */
293//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
294//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
295
296/*
297 * Agesa optional capabilities selection.
298 * Uncomment and mark FALSE those features you wish to include in the build.
299 * Comment out or mark TRUE those features you want to REMOVE from the build.
300 */
301
302#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
303#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
304#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
305#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
306#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
307#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
308#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
309#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
310#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
311#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
312#define DFLT_HPET_BASE_ADDRESS 0xFED00000
313#define DFLT_SMI_CMD_PORT 0xB0
314#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
315#define DFLT_GEC_BASE_ADDRESS 0xFED61000
316#define DFLT_AZALIA_SSID 0x780D1022
317#define DFLT_SMBUS_SSID 0x780B1022
318#define DFLT_IDE_SSID 0x780C1022
319#define DFLT_SATA_AHCI_SSID 0x78011022
320#define DFLT_SATA_IDE_SSID 0x78001022
321#define DFLT_SATA_RAID5_SSID 0x78031022
322#define DFLT_SATA_RAID_SSID 0x78021022
323#define DFLT_EHCI_SSID 0x78081022
324#define DFLT_OHCI_SSID 0x78071022
325#define DFLT_LPC_SSID 0x780E1022
326#define DFLT_SD_SSID 0x78061022
327#define DFLT_XHCI_SSID 0x78121022
328#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
329#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
330#define DFLT_FCH_GPP_LINK_CONFIG PortA4
331#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
332#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
333#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
334#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
335#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
336#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
337#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
338#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
339//#define BLDCFG_IR_PIN_CONTROL 0x33
340
Dave Frodind6aa7cf2014-11-21 14:57:03 -0700[diff] [blame]341GPIO_CONTROL gizmo2_gpio[] = {
Dave Frodinc43bce52014-12-03 08:22:46 -0700[diff] [blame]342 {183, Function1, GpioIn | GpioOutEnB | PullUpB},
343 {-1}
344};
Dave Frodind6aa7cf2014-11-21 14:57:03 -0700[diff] [blame]345//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&gizmo2_gpio[0])
Dave Frodinc43bce52014-12-03 08:22:46 -0700[diff] [blame]346
347// The following definitions specify the default values for various parameters in which there are
348// no clearly defined defaults to be used in the common file. The values below are based on product
349// and BKDG content, please consult the AGESA Memory team for consultation.
350#define DFLT_SCRUB_DRAM_RATE (0)
351#define DFLT_SCRUB_L2_RATE (0)
352#define DFLT_SCRUB_L3_RATE (0)
353#define DFLT_SCRUB_IC_RATE (0)
354#define DFLT_SCRUB_DC_RATE (0)
355#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
356#define DFLT_VRM_SLEW_RATE (5000)
357
358#include "PlatformInstall.h"
359
360/*----------------------------------------------------------------------------------------
361 * CUSTOMER OVERIDES MEMORY TABLE
362 *----------------------------------------------------------------------------------------
363 */
364
365/*
366 * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
367 * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
368 * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
369 * use its default conservative settings.
370 */
371CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
372 //
373 // The following macros are supported (use comma to separate macros):
374 //
375 // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
376 // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
377 // AGESA will base on this value to disable unused MemClk to save power.
378 // Example:
379 // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
380 // Bit AM3/S1g3 pin name
381 // 0 M[B,A]_CLK_H/L[0]
382 // 1 M[B,A]_CLK_H/L[1]
383 // 2 M[B,A]_CLK_H/L[2]
384 // 3 M[B,A]_CLK_H/L[3]
385 // 4 M[B,A]_CLK_H/L[4]
386 // 5 M[B,A]_CLK_H/L[5]
387 // 6 M[B,A]_CLK_H/L[6]
388 // 7 M[B,A]_CLK_H/L[7]
389 // And platform has the following routing:
390 // CS0 M[B,A]_CLK_H/L[4]
391 // CS1 M[B,A]_CLK_H/L[2]
392 // CS2 M[B,A]_CLK_H/L[3]
393 // CS3 M[B,A]_CLK_H/L[5]
394 // Then platform can specify the following macro:
395 // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
396 //
397 // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
398 // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
399 // AGESA will base on this value to tristate unused CKE to save power.
400 //
401 // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
402 // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
403 // AGESA will base on this value to tristate unused ODT pins to save power.
404 //
405 // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
406 // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
407 // AGESA will base on this value to tristate unused Chip select to save power.
408 //
409 // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
410 // Specifies the number of DIMM slots per channel.
411 //
412 // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
413 // Specifies the number of Chip selects per channel.
414 //
415 // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
416 // Specifies the number of channels per socket.
417 //
418 // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
419 // Specifies DDR bus speed of channel ChannelID on socket SocketID.
420 //
421 // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
422 // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
423 //
424 // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
425 // Byte6Seed, Byte7Seed, ByteEccSeed)
426 // Specifies the write leveling seed for a channel of a socket.
427 //
428 // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
429 // Byte6Seed, Byte7Seed, ByteEccSeed)
430 // Speicifes the HW RXEN training seed for a channel of a socket
431 //
Dave Frodind6aa7cf2014-11-21 14:57:03 -0700[diff] [blame]432
433 #define SEED_WL 0x0E
434 WRITE_LEVELING_SEED(
435 ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
436 SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,
437 SEED_WL),
438
Dave Frodinc43bce52014-12-03 08:22:46 -0700[diff] [blame]439 #define SEED_A 0x12
440 HW_RXEN_SEED(
441 ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
442 SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
443 SEED_A),
444
Dave Frodind6aa7cf2014-11-21 14:57:03 -0700[diff] [blame]445 NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
Dave Frodinc43bce52014-12-03 08:22:46 -0700[diff] [blame]446 NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
Dave Frodind6aa7cf2014-11-21 14:57:03 -0700[diff] [blame]447 MOTHER_BOARD_LAYERS (LAYERS_6),
Dave Frodinc43bce52014-12-03 08:22:46 -0700[diff] [blame]448
Dave Frodind6aa7cf2014-11-21 14:57:03 -0700[diff] [blame]449 MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
Dave Frodinc43bce52014-12-03 08:22:46 -0700[diff] [blame]450 CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
451 ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
452 CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
453
454 PSO_END
455};
456
457/*
458 * These tables are optional and may be used to adjust memory timing settings
459 */
460#include "mm.h"
461#include "mn.h"