blob: 8ffe09625643ecfb0fa0cff0798e0cdc17f750bb [file] [log] [blame]
Dave Frodin892d1292013-12-11 12:38:40 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 * Copyright (C) 2013 Sage Electronic Engineering, LLC
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Dave Frodin892d1292013-12-11 12:38:40 -070015 */
16
17/* DefinitionBlock Statement */
18DefinitionBlock (
19 "DSDT.AML", /* Output filename */
20 "DSDT", /* Signature */
21 0x02, /* DSDT Revision, needs to be 2 for 64bit */
22 "GIZSPH", /* OEMID */
23 "COREBOOT", /* TABLE ID */
24 0x00010001 /* OEM Revision */
25 )
26{ /* Start of ASL file */
27 /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
28
29 #include "acpi/mainboard.asl"
30
31 #include <cpu/amd/agesa/family14/acpi/cpu.asl>
32
33 #include "acpi/routing.asl"
34
35 Scope(\_SB) {
36 /* global utility methods expected within the \_SB scope */
37 #include <arch/x86/acpi/globutil.asl>
38
39 Device(PCI0) {
40
41 /* Describe the AMD Northbridge */
42 #include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
43
44 /* Describe the AMD Fusion Controller Hub Southbridge */
45 #include <southbridge/amd/cimx/sb800/acpi/fch.asl>
46
47 }
48 } /* End Scope(_SB) */
49
50 /* Contains the supported sleep states for this chipset */
51 #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
52
53 /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
54 #include "acpi/sleep.asl"
55
56 #include "acpi/gpe.asl"
Dave Frodin892d1292013-12-11 12:38:40 -070057}
58/* End of ASL file */