Damien Zammit | 4038a7f | 2015-04-20 16:53:36 +1000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Damien Zammit <damien@zamaudio.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Damien Zammit | 4038a7f | 2015-04-20 16:53:36 +1000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #define SUPERIO_BASE 0x2e |
| 17 | #define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0) |
| 18 | #define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) |
| 19 | #define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) |
| 20 | |
| 21 | #include <arch/io.h> |
| 22 | #include <device/pci_def.h> |
| 23 | #include <device/pnp_def.h> |
| 24 | #include <cpu/x86/lapic.h> |
| 25 | #include <arch/acpi.h> |
| 26 | #include <console/console.h> |
| 27 | #include <superio/ite/it8728f/it8728f.h> |
| 28 | #include <superio/ite/common/ite.h> |
| 29 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 30 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 31 | #include <southbridge/intel/bd82x6x/pch.h> |
| 32 | #include <southbridge/intel/bd82x6x/gpio.h> |
| 33 | #include <arch/cpu.h> |
| 34 | #include <cpu/x86/msr.h> |
| 35 | |
| 36 | static void it8728f_b75md3v_disable_reboot(device_t dev) |
| 37 | { |
| 38 | /* GPIO SIO settings */ |
| 39 | ite_reg_write(dev, 0xEF, 0x7E); // magic |
| 40 | |
| 41 | ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16 |
| 42 | ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34 |
| 43 | ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port |
| 44 | ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00 |
| 45 | ite_reg_write(dev, 0x72, 0x20); // watchdog timeout clear! |
| 46 | ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear! |
| 47 | ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in |
| 48 | ite_reg_write(dev, 0xe9, 0x27); // bus select disable |
| 49 | ite_reg_write(dev, 0xf0, 0x10); // ? |
| 50 | ite_reg_write(dev, 0xf1, 0x42); // ? |
| 51 | ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12) |
| 52 | |
| 53 | /* EC SIO settings */ |
| 54 | ite_reg_write(IT8728F_EC, 0xf1, 0xc0); |
| 55 | ite_reg_write(IT8728F_EC, 0xf6, 0xf0); |
| 56 | ite_reg_write(IT8728F_EC, 0xf9, 0x48); |
| 57 | ite_reg_write(IT8728F_EC, 0x60, 0x0a); |
| 58 | ite_reg_write(IT8728F_EC, 0x61, 0x30); |
| 59 | ite_reg_write(IT8728F_EC, 0x62, 0x0a); |
| 60 | ite_reg_write(IT8728F_EC, 0x63, 0x20); |
| 61 | ite_reg_write(IT8728F_EC, 0x30, 0x01); |
| 62 | } |
| 63 | |
| 64 | void rcba_config(void) |
| 65 | { |
| 66 | /* Disable unused devices (board specific) */ |
| 67 | RCBA32(FD) = 0x17ee1fe1; |
| 68 | |
| 69 | /* Enable HECI */ |
| 70 | RCBA32(FD2) &= ~0x2; |
| 71 | } |
| 72 | |
| 73 | void pch_enable_lpc(void) |
| 74 | { |
| 75 | /* |
| 76 | * Enable: |
| 77 | * EC Decode Range PortA30/A20 |
| 78 | * SuperIO Port2E/2F |
| 79 | * PS/2 Keyboard/Mouse Port60/64 |
| 80 | * FDD Port3F0h-3F5h and Port3F7h |
| 81 | */ |
| 82 | pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | |
| 83 | CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); |
| 84 | |
| 85 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); |
| 86 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); |
| 87 | |
| 88 | pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); |
| 89 | |
| 90 | /* Initialize SuperIO */ |
| 91 | ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 92 | it8728f_b75md3v_disable_reboot(SUPERIO_GPIO); |
| 93 | } |
| 94 | |
| 95 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 96 | { 1, 5, 0 }, |
| 97 | { 1, 5, 0 }, |
| 98 | { 1, 5, 1 }, |
| 99 | { 1, 5, 1 }, |
| 100 | { 1, 5, 2 }, |
| 101 | { 1, 5, 2 }, |
| 102 | { 1, 5, 3 }, |
| 103 | { 1, 5, 3 }, |
| 104 | { 1, 5, 4 }, |
| 105 | { 1, 5, 4 }, |
| 106 | { 1, 5, 6 }, |
| 107 | { 1, 5, 5 }, |
| 108 | { 1, 5, 5 }, |
| 109 | { 1, 5, 6 }, |
| 110 | }; |
| 111 | |
| 112 | void mainboard_get_spd(spd_raw_data *spd) { |
| 113 | read_spd (&spd[0], 0x50); |
| 114 | read_spd (&spd[1], 0x51); |
| 115 | read_spd (&spd[2], 0x52); |
| 116 | read_spd (&spd[3], 0x53); |
| 117 | } |