| Damien Zammit | 126a2a8 | 2014-11-28 15:59:10 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011-2012 Google Inc. |
| 6 | * Copyright (C) 2014 Vladimir Serbinenko |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| Damien Zammit | 126a2a8 | 2014-11-28 15:59:10 +1100 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <types.h> |
| 19 | #include <string.h> |
| 20 | #include <device/device.h> |
| 21 | #include <device/pci_def.h> |
| 22 | #include <device/pci_ops.h> |
| 23 | #include <console/console.h> |
| 24 | #include <drivers/intel/gma/int15.h> |
| 25 | #include <pc80/mc146818rtc.h> |
| 26 | #include <arch/acpi.h> |
| 27 | #include <arch/io.h> |
| 28 | #include <arch/interrupt.h> |
| 29 | #include <boot/coreboot_tables.h> |
| 30 | #include <southbridge/intel/bd82x6x/pch.h> |
| 31 | #include <smbios.h> |
| 32 | #include <device/pci.h> |
| 33 | #include <cbfs.h> |
| Damien Zammit | 126a2a8 | 2014-11-28 15:59:10 +1100 | [diff] [blame] | 34 | |
| Damien Zammit | 126a2a8 | 2014-11-28 15:59:10 +1100 | [diff] [blame] | 35 | static void mainboard_init(device_t dev) |
| 36 | { |
| 37 | RCBA32(0x38c8) = 0x00002005; |
| 38 | RCBA32(0x38c4) = 0x00802005; |
| 39 | RCBA32(0x38c0) = 0x00000007; |
| 40 | RCBA32(0x2240) = 0x00330e71; |
| 41 | RCBA32(0x2244) = 0x003f0eb1; |
| 42 | RCBA32(0x2248) = 0x002102cd; |
| 43 | RCBA32(0x224c) = 0x00f60000; |
| 44 | RCBA32(0x2250) = 0x00020000; |
| 45 | RCBA32(0x2254) = 0x00e3004c; |
| 46 | RCBA32(0x2258) = 0x00e20bef; |
| 47 | RCBA32(0x2260) = 0x003304ed; |
| 48 | RCBA32(0x2278) = 0x001107c1; |
| 49 | RCBA32(0x227c) = 0x001d07e9; |
| 50 | RCBA32(0x2280) = 0x00e20000; |
| 51 | RCBA32(0x2284) = 0x00ee0000; |
| 52 | RCBA32(0x2288) = 0x005b05d3; |
| 53 | RCBA32(0x2318) = 0x04b8ff2e; |
| 54 | RCBA32(0x231c) = 0x03930f2e; |
| 55 | RCBA32(0x3808) = 0x005044a3; |
| 56 | RCBA32(0x3810) = 0x52410000; |
| 57 | RCBA32(0x3814) = 0x0000008a; |
| 58 | RCBA32(0x3818) = 0x00000006; |
| 59 | RCBA32(0x381c) = 0x0000072e; |
| 60 | RCBA32(0x3820) = 0x0000000a; |
| 61 | RCBA32(0x3824) = 0x00000123; |
| 62 | RCBA32(0x3828) = 0x00000009; |
| 63 | RCBA32(0x382c) = 0x00000001; |
| 64 | RCBA32(0x3834) = 0x0000061a; |
| 65 | RCBA32(0x3838) = 0x00000003; |
| 66 | RCBA32(0x383c) = 0x00000a76; |
| 67 | RCBA32(0x3840) = 0x00000004; |
| 68 | RCBA32(0x3844) = 0x0000e5e4; |
| 69 | RCBA32(0x3848) = 0x0000000e; |
| 70 | } |
| 71 | |
| 72 | // mainboard_enable is executed as first thing after |
| 73 | // enumerate_buses(). |
| 74 | |
| 75 | static void mainboard_enable(device_t dev) |
| 76 | { |
| 77 | dev->ops->init = mainboard_init; |
| 78 | |
| 79 | install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0); |
| 80 | } |
| 81 | |
| 82 | struct chip_operations mainboard_ops = { |
| 83 | .enable_dev = mainboard_enable, |
| 84 | }; |