| Michael Tasche | 446c5dc | 2015-12-03 17:07:01 +0100 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
| 5 | ## Copyright (C) 2014 Intel Corporation |
| 6 | ## |
| 7 | ## This program is free software; you can redistribute it and/or modify |
| 8 | ## it under the terms of the GNU General Public License as published by |
| 9 | ## the Free Software Foundation; version 2 of the License. |
| 10 | ## |
| 11 | ## This program is distributed in the hope that it will be useful, |
| 12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | ## GNU General Public License for more details. |
| 15 | ## |
| 16 | |
| 17 | chip soc/intel/fsp_baytrail |
| 18 | |
| 19 | #### ACPI Register Settings #### |
| 20 | register "fadt_pm_profile" = "PM_UNSPECIFIED" |
| 21 | register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" |
| 22 | |
| 23 | #### FSP register settings #### |
| 24 | register "PcdSataMode" = "SATA_MODE_AHCI" |
| 25 | register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" |
| 26 | register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" |
| 27 | register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT" |
| 28 | register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" |
| 29 | register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" |
| 30 | register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT" |
| 31 | register "PcdGttSize" = "GTT_SIZE_DEFAULT" |
| 32 | register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" |
| 33 | register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" |
| 34 | register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" |
| 35 | register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE" |
| 36 | register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE" |
| 37 | register "DRAMSpeed" = "DRAM_SPEED_1066MHZ" |
| 38 | register "DRAMType" = "DRAM_TYPE_DDR3L" |
| 39 | register "DIMM0Enable" = "DIMM0_ENABLE" |
| 40 | register "DIMM1Enable" = "DIMM1_DISABLE" |
| 41 | register "DIMMDWidth" = "DIMM_DWIDTH_X16" |
| 42 | register "DIMMDensity" = "DIMM_DENSITY_4G_BIT" |
| 43 | register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT" |
| 44 | register "DIMMSides" = "DIMM_SIDES_1RANK" |
| 45 | register "DIMMtCL" = "8" |
| 46 | register "DIMMtRPtRCD" = "8" |
| 47 | register "DIMMtWR" = "8" |
| 48 | register "DIMMtWTR" = "4" |
| 49 | register "DIMMtRRD" = "6" |
| 50 | register "DIMMtRTP" = "4" |
| 51 | register "DIMMtFAW" = "27" |
| 52 | |
| 53 | device cpu_cluster 0 on |
| 54 | device lapic 0 on end |
| 55 | end |
| 56 | |
| 57 | device domain 0 on |
| 58 | device pci 00.0 on end # 8086 0F00 - SoC router - |
| 59 | device pci 02.0 off end # 8086 0F31 - GFX - |
| 60 | device pci 03.0 off end # 8086 0F38 - MIPI - |
| 61 | |
| 62 | device pci 10.0 off end # 8086 0F14 - EMMC Port - |
| 63 | device pci 11.0 off end # 8086 0F15 - SDIO Port - |
| 64 | device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3 |
| 65 | device pci 13.0 off end # 8086 0F23 - SATA AHCI - |
| 66 | device pci 14.0 off end # 8086 0F35 - USB XHCI - |
| 67 | device pci 15.0 off end # 8086 0F28 - LP Engine Audio - |
| 68 | device pci 17.0 off end # 8086 0F50 - MMC Port - |
| 69 | device pci 18.0 on end # 8086 0F40 - SIO - DMA - |
| 70 | device pci 18.1 on end # 8086 0F41 - I2C Port 1 (0) - |
| 71 | device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) - |
| 72 | device pci 18.3 on end # 8086 0F43 - I2C Port 3 (2) - |
| 73 | device pci 18.4 on end # 8086 0F44 - I2C Port 4 (3) - |
| 74 | device pci 18.5 on end # 8086 0F45 - I2C Port 5 (4) - |
| 75 | device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) EEPROM |
| 76 | device pci 18.7 off end # 8086 0F47 - I2C Port 7 (6) - |
| 77 | device pci 1a.0 off end # 8086 0F18 - TXE - |
| 78 | device pci 1b.0 off end # 8086 0F04 - HD Audio - |
| 79 | device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) - |
| 80 | device pci 1c.1 off end # 8086 0F4A - PCIe Port 2 (1) - |
| 81 | device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) ETHERNET |
| 82 | device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) CAN |
| 83 | device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling EHCI - |
| 84 | device pci 1e.0 on end # 8086 0F06 - SIO - DMA - |
| 85 | device pci 1e.1 on end # 8086 0F08 - PWM 1 - |
| 86 | device pci 1e.2 on end # 8086 0F09 - PWM 2 - |
| 87 | device pci 1e.3 on end # 8086 0F0A - HSUART 1 Alternate uart |
| 88 | device pci 1e.4 off end # 8086 0F0C - HSUART 2 - |
| 89 | device pci 1e.5 off end # 8086 0F0E - SPI - |
| 90 | device pci 1f.0 on end # 8086 0F1C - LPC bridge No connector |
| 91 | device pci 1f.3 on end # 8086 0F12 - SMBus 0 SPC |
| 92 | end |
| 93 | end |