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Kyösti Mälkki595ef3d2015-05-27 12:44:16 +03001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Kyösti Mälkki595ef3d2015-05-27 12:44:16 +030014 */
15
16#include "AGESA.h"
17#include "amdlib.h"
18#include <northbridge/amd/agesa/BiosCallOuts.h>
19#include "Ids.h"
20#include "OptionsIds.h"
21#include "heapManager.h"
22#include "FchPlatform.h"
23#include "cbfs.h"
24#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
25#include "imc.h"
26#endif
27#include <stdlib.h>
28
Stefan Reinauerdd132a52015-07-30 11:16:37 -070029static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
Kyösti Mälkki595ef3d2015-05-27 12:44:16 +030030
31const BIOS_CALLOUT_STRUCT BiosCallouts[] =
32{
33 {AGESA_DO_RESET, agesa_Reset },
34 {AGESA_READ_SPD, agesa_ReadSpd_from_cbfs },
35 {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
36 {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
37 {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
38 {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
39 {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
40 {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config },
41 {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
42};
43const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
44
45/**
46 * ALC272 Verb Table
47 */
48const CODEC_ENTRY Alc272_VerbTbl[] = {
49 {0x11, 0x411111F0}, // - SPDIF_OUT2
50 {0x12, 0x411111F0}, // - DMIC_1/2
51 {0x13, 0x411111F0}, // - DMIC_3/4
52 {0x14, 0x411111F0}, // Port D - LOUT1
53 {0x15, 0x01011050}, // Port A - LOUT2 Explorer 2x DAC
54 {0x16, 0x411111F0}, //
55 {0x17, 0x411111F0}, // Port H - MONO
56 {0x18, 0x01a11840}, // Port B - MIC1
57 {0x19, 0x411111F0}, // Port F - MIC2
58 {0x1a, 0x01811030}, // Port C - LINE1
59 {0x1b, 0x01811020}, // Port E - LINE2 Explorer 2x ADC
60 {0x1d, 0x40130605}, // - PCBEEP
61 {0x1e, 0x411111F0}, // - SPDIF_OUT1
62 {0x21, 0x01211010}, // Port I - HPOUT
63 {0xff, 0xffffffff}
64};
65
66static const CODEC_TBL_LIST CodecTableList[] =
67{
68 {0x10ec0272, (CODEC_ENTRY*)&Alc272_VerbTbl[0]},
69 {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
70};
71
72#define FAN_INPUT_INTERNAL_DIODE 0
73#define FAN_INPUT_TEMP0 1
74#define FAN_INPUT_TEMP1 2
75#define FAN_INPUT_TEMP2 3
76#define FAN_INPUT_TEMP3 4
77#define FAN_INPUT_TEMP0_FILTER 5
78#define FAN_INPUT_ZERO 6
79#define FAN_INPUT_DISABLED 7
80
81#define FAN_AUTOMODE (1 << 0)
82#define FAN_LINEARMODE (1 << 1)
83#define FAN_STEPMODE ~(1 << 1)
84#define FAN_POLARITY_HIGH (1 << 2)
85#define FAN_POLARITY_LOW ~(1 << 2)
86
87/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
88#define FREQ_28KHZ 0x0
89#define FREQ_25KHZ 0x1
90#define FREQ_23KHZ 0x2
91#define FREQ_21KHZ 0x3
92#define FREQ_29KHZ 0x4
93#define FREQ_18KHZ 0x5
94#define FREQ_100HZ 0xF7
95#define FREQ_87HZ 0xF8
96#define FREQ_58HZ 0xF9
97#define FREQ_44HZ 0xFA
98#define FREQ_35HZ 0xFB
99#define FREQ_29HZ 0xFC
100#define FREQ_22HZ 0xFD
101#define FREQ_14HZ 0xFE
102#define FREQ_11HZ 0xFF
103
104/* Hardware Monitor Fan Control
105 * Hardware limitation:
106 * HWM failed to read the input temperture vi I2C,
107 * if other software switch the I2C switch by mistake or intention.
108 * We recommend to using IMC to control Fans, instead of HWM.
109 */
110static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
111{
112 /* Enable IMC fan control. the recommand way */
113#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
114
115 imc_reg_init();
116
117 /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
118 FchParams->Hwm.HwMonitorEnable = TRUE;
119 FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */
120
121 FchParams->Imc.ImcEnable = TRUE;
122 FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
123 FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
124
125 LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
126
127 /* Thermal Zone Parameter */
128 FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
129 FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
130 FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5;
131 FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3;
132 FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
133 FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04;
134 FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
135 FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01;
136 FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */
137 FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00;
138
139 /* IMC Fan Policy temperature thresholds */
140 FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
141 FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
142 FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 50; /*AC0 threshold in Celsius */
143 FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 45; /*AC1 threshold in Celsius */
144 FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 40; /*AC2 threshold in Celsius */
145 FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */
146 FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */
147 FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */
148 FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */
149 FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */
150 FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */
151 FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
152
153 /* IMC Fan Policy PWM Settings */
154 FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
155 FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */
156 FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 100; /* AL0 percentage */
157 FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 99; /* AL1 percentage */
158 FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 98; /* AL2 percentage */
159 FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */
160 FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */
161 FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */
162 FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */
163 FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */
164
165 FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8;
166
167 /* NOTE:
168 * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege,
169 * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it.
170 * so we remove it from AGESA code. Please Seee FchInitLateHwm.
171 */
172
173#else /* HWM fan control, the way not recommand */
174 FchParams->Imc.ImcEnable = FALSE;
175 FchParams->Hwm.HwMonitorEnable = TRUE;
176 FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */
177
178#endif /* CONFIG_HUDSON_IMC_FWM */
179}
180
181/**
182 * Fch Oem setting callback
183 *
184 * Configure platform specific Hudson device,
185 * such Azalia, SATA, IMC etc.
186 */
Stefan Reinauerdd132a52015-07-30 11:16:37 -0700187static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
Kyösti Mälkki595ef3d2015-05-27 12:44:16 +0300188{
189 AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
190
191 if (StdHeader->Func == AMD_INIT_RESET) {
192 FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
193 printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
194 //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
195 FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
196 FchParams_reset->FchReset.Xhci1Enable = FALSE;
197 } else if (StdHeader->Func == AMD_INIT_ENV) {
198 FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
199 printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
200
201 /* Azalia Controller OEM Codec Table Pointer */
202 FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
203 /* Azalia Controller Front Panel OEM Table Pointer */
204
205 /* Fan Control */
206 oem_fan_control(FchParams_env);
207
208 /* XHCI configuration */
209 FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
210 FchParams_env->Usb.Xhci1Enable = FALSE;
211
212 /* sata configuration */
213 }
214 printk(BIOS_DEBUG, "Done\n");
215
216 return AGESA_SUCCESS;
217}