Christian Gmeiner | 86f992c | 2012-07-13 11:36:08 +0200 | [diff] [blame] | 1 | chip northbridge/amd/lx |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 2 | device domain 0 on |
Christian Gmeiner | 86f992c | 2012-07-13 11:36:08 +0200 | [diff] [blame] | 3 | device pci 1.0 on end # Northbridge |
| 4 | device pci 1.1 on end # Graphics |
| 5 | device pci 1.2 on end # AES |
| 6 | chip southbridge/amd/cs5536 |
| 7 | register "lpc_serirq_enable" = "0x00000000" |
| 8 | register "lpc_serirq_polarity" = "0x00000000" |
| 9 | register "lpc_serirq_mode" = "0" |
| 10 | register "enable_gpio_int_route" = "0x0C0D0700" |
| 11 | register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash |
| 12 | register "enable_USBP4_device" = "0" #0: host, 1:device |
| 13 | register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) |
| 14 | register "com1_enable" = "1" |
| 15 | register "com1_address" = "0x3F8" |
| 16 | register "com1_irq" = "4" |
| 17 | register "com2_enable" = "1" |
| 18 | register "com2_address" = "0x2F8" |
| 19 | register "com2_irq" = "3" |
| 20 | register "unwanted_vpci[0]" = "0" # End of list has a zero |
| 21 | device pci 4.0 on end # Ethernet 0 |
Christian Gmeiner | ea8011b | 2012-09-14 16:28:44 +0200 | [diff] [blame] | 22 | device pci f.0 on # ISA Bridge |
| 23 | chip drivers/generic/generic # eeprom |
| 24 | device i2c 52 on end |
| 25 | end |
| 26 | end |
Christian Gmeiner | 86f992c | 2012-07-13 11:36:08 +0200 | [diff] [blame] | 27 | device pci f.2 on end # IDE Controller |
| 28 | device pci f.3 on end # Audio |
| 29 | device pci f.4 on end # OHCI |
| 30 | device pci f.5 on end # EHCI |
| 31 | device pci f.7 on end # UOC |
| 32 | end |
| 33 | end |
| 34 | # APIC cluster is late CPU init. |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 35 | device cpu_cluster 0 on |
Christian Gmeiner | 86f992c | 2012-07-13 11:36:08 +0200 | [diff] [blame] | 36 | chip cpu/amd/geode_lx |
| 37 | device lapic 0 on end |
| 38 | end |
| 39 | end |
| 40 | end |