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Corey Osgoode99bd102007-06-14 06:10:57 +00001#include <arch/pirq_routing.h>
2
Stefan Reinauera47bd912012-11-15 15:15:15 -08003static const struct irq_routing_table intel_irq_routing_table = {
Corey Osgoode99bd102007-06-14 06:10:57 +00004 PIRQ_SIGNATURE, /* u32 signature */
5 PIRQ_VERSION, /* u16 version */
Uwe Hermann95313d82009-10-07 21:51:33 +00006 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
Corey Osgoode99bd102007-06-14 06:10:57 +00007 0x00, /* Where the interrupt router lies (bus) */
8 (0x11<<3)|0x0, /* Where the interrupt router lies (dev) */
9 0xe20, /* IRQs devoted exclusively to PCI usage */
10 0x8086, /* Vendor */
11 0x7120, /* Device */
Uwe Hermann8fa90ec2010-09-21 21:16:27 +000012 0, /* Miniport data */
Corey Osgoode99bd102007-06-14 06:10:57 +000013 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
Stefan Reinauer14e22772010-04-27 06:56:47 +000014 0x89, /* u8 checksum , this has to set to some value
Corey Osgoode99bd102007-06-14 06:10:57 +000015that would give 0 after the sum of all bytes for this structure (including checksum) */
16 {
17 /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
18 {0x00,(0x08<<3)|0x0, {{0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0x0dea0}}, 0x1, 0x0},
19 {0x00,(0x09<<3)|0x0, {{0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0x0dea0}}, 0x2, 0x0},
20 {0x00,(0x0a<<3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x3, 0x0},
21 {0x00,(0x0b<<3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x4, 0x0},
22 {0x00,(0x0c<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x5, 0x0},
23 {0x00,(0x0d<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x6, 0x0},
24 {0x00,(0x11<<3)|0x0, {{0x00, 0xdea0}, {0x00, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0},
25 {0x00,(0x0f<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0},
26 {0x00,(0x01<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0},
27 {0x00,(0x10<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0},
28 {0x00,(0x12<<3)|0x0, {{0x01, 0xdea0}, {0x00, 0xdea0}, {0x00, 0xdea0}, {0x00, 0x0dea0}}, 0x0, 0x0},
29 }
30};
31
32unsigned long write_pirq_routing_table(unsigned long addr)
33{
Stefan Reinauera47bd912012-11-15 15:15:15 -080034 return copy_pirq_routing_table(addr, &intel_irq_routing_table);
Corey Osgoode99bd102007-06-14 06:10:57 +000035}