Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2006 AMD |
| 5 | * (Written by Yinghai Lu <yinghailu@amd.com> for AMD) |
| 6 | * Copyright (C) 2006 MSI |
| 7 | * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI) |
| 8 | * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz> |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 19 | */ |
| 20 | |
| 21 | unsigned int get_sbdn(unsigned bus); |
| 22 | |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 23 | #include <stdint.h> |
| 24 | #include <string.h> |
| 25 | #include <device/pci_def.h> |
| 26 | #include <arch/io.h> |
| 27 | #include <device/pnp_def.h> |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 28 | #include <cpu/amd/mtrr.h> |
| 29 | #include <cpu/x86/lapic.h> |
| 30 | #include <pc80/mc146818rtc.h> |
| 31 | #include <console/console.h> |
| 32 | #include <cpu/amd/model_fxx_rev.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 33 | #include <halt.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 34 | #include <northbridge/amd/amdk8/raminit.h> |
Edward O'Callaghan | ebe3a7a | 2015-01-05 00:27:54 +1100 | [diff] [blame] | 35 | #include <delay.h> |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 36 | #include "northbridge/amd/amdk8/reset_test.c" |
| 37 | #include "northbridge/amd/amdk8/debug.c" |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 38 | #include <superio/ite/common/ite.h> |
| 39 | #include <superio/ite/it8712f/it8712f.h> |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 40 | #include "southbridge/via/vt8237r/early_smbus.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 41 | #include <cpu/x86/bist.h> |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 42 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
Uwe Hermann | 6dc92f0 | 2010-11-21 11:36:03 +0000 | [diff] [blame] | 43 | #include <spd.h> |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 44 | |
| 45 | #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) |
Edward O'Callaghan | 76d8fd6 | 2014-05-14 19:15:08 +1000 | [diff] [blame] | 46 | #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 47 | #define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO) |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 48 | |
| 49 | #define IT8712F_GPIO_BASE 0x0a20 |
| 50 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 51 | static void memreset(int controllers, const struct mem_controller *ctrl) { } |
| 52 | static void activate_spd_rom(const struct mem_controller *ctrl) { } |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 53 | |
| 54 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 55 | { |
| 56 | return smbus_read_byte(device, address); |
| 57 | } |
| 58 | |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 59 | #include "southbridge/via/k8t890/early_car.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 60 | #include <northbridge/amd/amdk8/amdk8.h> |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 61 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
| 62 | #include "northbridge/amd/amdk8/coherent_ht.c" |
| 63 | #include "northbridge/amd/amdk8/raminit_f.c" |
| 64 | #include "lib/generic_sdram.c" |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 65 | #include "cpu/amd/dualcore/dualcore.c" |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 66 | #include "cpu/amd/model_fxx/init_cpus.c" |
| 67 | #include "cpu/amd/model_fxx/fidvid.c" |
| 68 | #include "northbridge/amd/amdk8/resourcemap.c" |
| 69 | |
| 70 | void soft_reset(void) |
| 71 | { |
| 72 | uint8_t tmp; |
| 73 | |
| 74 | set_bios_reset(); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 75 | printk(BIOS_DEBUG, "soft reset\n"); |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 76 | |
| 77 | /* PCI reset */ |
| 78 | tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); |
| 79 | tmp |= 0x01; |
| 80 | /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */ |
| 81 | pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); |
| 82 | |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 83 | halt(); |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 84 | } |
| 85 | |
| 86 | unsigned int get_sbdn(unsigned bus) |
| 87 | { |
| 88 | device_t dev; |
| 89 | |
| 90 | dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, |
| 91 | PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); |
| 92 | return (dev >> 15) & 0x1f; |
| 93 | } |
| 94 | |
| 95 | struct gpio_init_val { |
| 96 | u8 addr; |
| 97 | u8 val; |
| 98 | }; |
| 99 | |
| 100 | static const struct gpio_init_val gpio_init_data[] = { |
| 101 | /* multi-function pin selection */ |
| 102 | { 0x25, 0x00 }, |
| 103 | { 0x28, 0x00 }, /* gp46 is infrared receive input */ |
| 104 | { 0x29, 0x40 }, /* reserved value?!? */ |
| 105 | { 0x2a, 0x00 }, |
| 106 | { 0x2c, 0x1d }, /* pin91 is VIN7 instead of PCIRSTIN# */ |
| 107 | /* gpio i/o port base */ |
| 108 | { 0x62, IT8712F_GPIO_BASE >> 8 }, |
| 109 | { 0x63, IT8712F_GPIO_BASE & 0xff }, |
| 110 | /* 0xb8 - 0xbc: gpio pull-up enable */ |
| 111 | { 0xb8, 0x00 }, |
| 112 | /* 0xc0 - 0xc4: gpio alternate function select */ |
| 113 | { 0xc0, 0x00 }, |
| 114 | { 0xc3, 0x00 }, |
| 115 | { 0xc4, 0xc0 }, |
| 116 | /* 0xc8 - 0xcc: gpio output enable */ |
| 117 | { 0xc8, 0x00 }, |
| 118 | { 0xcb, 0x00 }, |
| 119 | { 0xcc, 0xc0 }, |
| 120 | /* end of list */ |
| 121 | { 0, 0 }, |
| 122 | }; |
| 123 | |
| 124 | static void m2v_it8712f_gpio_init(void) |
| 125 | { |
| 126 | const struct gpio_init_val *giv; |
| 127 | |
| 128 | printk(BIOS_SPEW, "it8712f gpio init...\n"); |
| 129 | |
| 130 | /* |
| 131 | * it8712f gpio config |
| 132 | * |
| 133 | * Most importantly this switches pin 91 from |
| 134 | * PCIRSTIN# to VIN7. |
| 135 | * Note that only PCIRST3# and PCIRST5# are affected |
| 136 | * by PCIRSTIN#, the PCIRST1#, PCIRST2#, PCIRST4# are always |
| 137 | * direct buffers of #LRESET (low pin count bus reset). |
| 138 | * If this is not done All PCIRST are in reset state and the |
| 139 | * pcie slots don't initialize. |
| 140 | * |
| 141 | * pci reset handling: |
| 142 | * pin 91: VIN7 (alternate PCIRSTIN#) |
| 143 | * pin 48: PCIRST5# / gpio port 5 bit 0 |
| 144 | * pin 84: PCIRST4# / gpio port 1 bit 0 |
| 145 | * pin 31: PCIRST1# / gpio port 1 bit 4 |
| 146 | * pin 33: PCIRST2# / gpio port 1 bit 2 |
| 147 | * pin 34: PCIRST3# / gpio port 1 bit 1 |
| 148 | * |
| 149 | * PCIRST[0-5]# are connected as follows: |
| 150 | * pcirst1# -> pci bus |
| 151 | * pcirst2# -> ide bus |
| 152 | * pcirst3# -> pcie devices |
| 153 | * pcirst4# -> pcie graphics |
| 154 | * pcirst5# -> maybe n/c (untested) |
| 155 | * |
| 156 | * For software control of PCIRST[1-5]#: |
| 157 | * 0x2a=0x17 (deselect pcirst# hardwiring, enable 0x25 control) |
| 158 | * 0x25=0x17 (select gpio function) |
| 159 | * 0xc0=0x17, 0xc8=0x17 gpio port 1 select & output enable |
| 160 | * 0xc4=0xc1, 0xcc=0xc1 gpio port 5 select & output enable |
| 161 | */ |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 162 | giv = gpio_init_data; |
| 163 | while (giv->addr) { |
| 164 | printk(BIOS_SPEW, "it8712f gpio: %02x=%02x\n", |
| 165 | giv->addr, giv->val); |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 166 | ite_reg_write(IT8712F_GPIO, giv->addr, giv->val); |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 167 | giv++; |
| 168 | } |
Tobias Diedrich | 5960fb3 | 2010-11-12 20:46:02 +0000 | [diff] [blame] | 169 | |
| 170 | printk(BIOS_INFO, "it8712f gpio: Setting DDR2 voltage to 1.80V\n"); |
| 171 | /* |
| 172 | * upper two bits of gpio_base+4 control ddr2 voltage: |
| 173 | * 11: 1.80V |
| 174 | * 01: 1.85V |
| 175 | * 10: 1.90V |
| 176 | * 00: 1.95V |
| 177 | * |
| 178 | * The lower six bits are inputs and normally read back as 1 |
| 179 | * (except bit 2, which seems rather random). |
| 180 | */ |
| 181 | outb(0xff, IT8712F_GPIO_BASE+4); |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 182 | } |
| 183 | |
| 184 | static void m2v_bus_init(void) |
| 185 | { |
| 186 | device_t dev; |
| 187 | |
| 188 | printk(BIOS_SPEW, "m2v_bus_init\n"); |
| 189 | |
| 190 | dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, |
| 191 | PCI_DEVICE_ID_VIA_K8T890CF_0), 0); |
| 192 | pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01); |
| 193 | |
| 194 | dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, |
| 195 | PCI_DEVICE_ID_VIA_K8T890CF_5), 0); |
| 196 | /* |
| 197 | * bit | meaning |
| 198 | * 6 | 0: hide scratch register function 0:0.6 (we don't use it) |
| 199 | * 5 | 1: enable pcie bridge 0:2.0 |
| 200 | * 4 | 0: hide pcie bridge 0:3.3 (not connected) |
| 201 | * 3 | 1: enable pcie bridge 0:3.2 |
| 202 | * 2 | 1: enable pcie bridge 0:3.1 |
| 203 | * 1 | 1: enable pcie bridge 0:3.0 |
| 204 | */ |
| 205 | pci_write_config8(dev, 0xf0, 0x2e); |
| 206 | } |
| 207 | |
| 208 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 209 | { |
| 210 | static const uint16_t spd_addr[] = { |
| 211 | // Node 0 |
Uwe Hermann | 6dc92f0 | 2010-11-21 11:36:03 +0000 | [diff] [blame] | 212 | DIMM0, DIMM2, 0, 0, |
| 213 | DIMM1, DIMM3, 0, 0, |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 214 | // Node 1 |
Uwe Hermann | 6dc92f0 | 2010-11-21 11:36:03 +0000 | [diff] [blame] | 215 | DIMM4, DIMM6, 0, 0, |
| 216 | DIMM5, DIMM7, 0, 0, |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 217 | }; |
| 218 | unsigned bsp_apicid = 0; |
| 219 | int needs_reset = 0; |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 220 | struct sys_info *sysinfo = &sysinfo_car; |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 221 | |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 222 | ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); |
| 223 | ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Edward O'Callaghan | 76d8fd6 | 2014-05-14 19:15:08 +1000 | [diff] [blame] | 224 | ite_kill_watchdog(GPIO_DEV); |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 225 | console_init(); |
| 226 | enable_rom_decode(); |
| 227 | m2v_bus_init(); |
| 228 | m2v_it8712f_gpio_init(); |
Edward O'Callaghan | 76d8fd6 | 2014-05-14 19:15:08 +1000 | [diff] [blame] | 229 | ite_enable_3vsbsw(GPIO_DEV); |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 230 | |
Elyes HAOUAS | aedcc10 | 2014-07-21 08:07:19 +0200 | [diff] [blame] | 231 | printk(BIOS_INFO, "now booting...\n"); |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 232 | |
| 233 | if (bist == 0) |
| 234 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
| 235 | |
| 236 | /* Halt if there was a built in self test failure. */ |
| 237 | report_bist_failure(bist); |
| 238 | setup_default_resource_map(); |
| 239 | setup_coherent_ht_domain(); |
| 240 | wait_all_core0_started(); |
| 241 | |
| 242 | printk(BIOS_INFO, "now booting... All core 0 started\n"); |
| 243 | |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 244 | #if CONFIG_LOGICAL_CPUS |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 245 | /* It is said that we should start core1 after all core0 launched. */ |
| 246 | start_other_cores(); |
| 247 | wait_all_other_cores_started(bsp_apicid); |
| 248 | #endif |
| 249 | init_timer(); |
| 250 | ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ |
| 251 | |
| 252 | needs_reset = optimize_link_coherent_ht(); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 253 | printk(BIOS_DEBUG, "%02x", needs_reset); |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 254 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 255 | printk(BIOS_DEBUG, "%02x", needs_reset); |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 256 | needs_reset |= k8t890_early_setup_ht(); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 257 | printk(BIOS_DEBUG, "%02x", needs_reset); |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 258 | |
| 259 | if (needs_reset) { |
| 260 | printk(BIOS_DEBUG, "ht reset -\n"); |
| 261 | soft_reset(); |
| 262 | printk(BIOS_DEBUG, "FAILED!\n"); |
| 263 | } |
| 264 | |
| 265 | /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ |
| 266 | /* allow LDT STOP asserts */ |
| 267 | vt8237_sb_enable_fid_vid(); |
| 268 | |
| 269 | enable_fid_change(); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 270 | printk(BIOS_DEBUG, "after enable_fid_change\n"); |
Tobias Diedrich | 4e6305f | 2010-11-07 20:08:45 +0000 | [diff] [blame] | 271 | |
| 272 | init_fidvid_bsp(bsp_apicid); |
| 273 | |
| 274 | /* Stop the APs so we can start them later in init. */ |
| 275 | allow_all_aps_stop(bsp_apicid); |
| 276 | |
| 277 | /* It's the time to set ctrl now. */ |
| 278 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 279 | enable_smbus(); |
| 280 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 281 | post_cache_as_ram(); |
| 282 | } |