Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
| 5 | * |
| 6 | * Copyright (C) 2007 AMD |
| 7 | * Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include <stdint.h> |
| 21 | #include <string.h> |
| 22 | #include <reset.h> |
| 23 | #include <device/pci_def.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | #include <arch/io.h> |
| 26 | #include <device/pnp_def.h> |
| 27 | #include <cpu/x86/lapic.h> |
| 28 | #include <console/console.h> |
| 29 | #include <timestamp.h> |
| 30 | #include <lib.h> |
| 31 | #include <spd.h> |
| 32 | #include <cpu/amd/model_10xxx_rev.h> |
| 33 | #include <northbridge/amd/amdfam10/raminit.h> |
| 34 | #include <northbridge/amd/amdfam10/amdfam10.h> |
| 35 | #include "lib/delay.c" |
| 36 | #include <cpu/x86/lapic.h> |
| 37 | #include "northbridge/amd/amdfam10/reset_test.c" |
| 38 | #include <superio/nuvoton/common/nuvoton.h> |
| 39 | #include <superio/nuvoton/nct5572d/nct5572d.h> |
| 40 | #include <cpu/x86/bist.h> |
Timothy Pearson | e619a9a | 2015-09-05 19:37:57 -0500 | [diff] [blame] | 41 | #include <smp/spinlock.h> |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 42 | // #include "northbridge/amd/amdk8/incoherent_ht.c" |
| 43 | #include <southbridge/amd/sb700/sb700.h> |
| 44 | #include <southbridge/amd/sb700/smbus.h> |
| 45 | #include <southbridge/amd/sr5650/sr5650.h> |
| 46 | #include "northbridge/amd/amdfam10/debug.c" |
| 47 | #include "northbridge/amd/amdfam10/setup_resource_map.c" |
| 48 | |
| 49 | #define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1) |
| 50 | |
| 51 | static void activate_spd_rom(const struct mem_controller *ctrl); |
| 52 | |
| 53 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 54 | { |
| 55 | return do_smbus_read_byte(SMBUS_AUX_IO_BASE, device, address); |
| 56 | } |
| 57 | |
| 58 | #include <northbridge/amd/amdfam10/amdfam10.h> |
| 59 | #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" |
| 60 | #include "northbridge/amd/amdfam10/pci.c" |
| 61 | #include "resourcemap.c" |
| 62 | #include "cpu/amd/quadcore/quadcore.c" |
| 63 | |
| 64 | #include <cpu/amd/microcode.h> |
| 65 | |
Timothy Pearson | b30d7ed | 2015-10-16 14:24:06 -0500 | [diff] [blame] | 66 | #include "cpu/amd/family_10h-family_15h/init_cpus.c" |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 67 | #include "northbridge/amd/amdfam10/early_ht.c" |
| 68 | |
| 69 | /* |
| 70 | * ASUS KGPE-D16 specific SPD enable/disable magic. |
| 71 | * |
| 72 | * Setting SP5100 GPIOs 59 and 60 controls an SPI mux with four settings: |
| 73 | * 0: Disabled |
| 74 | * 1: Normal SPI access |
| 75 | * 2: CPU0 SPD |
| 76 | * 3: CPU1 SPD |
| 77 | * |
| 78 | * Disable SPD access after RAM init to allow access to standard SMBus/I2C offsets |
| 79 | * which is required e.g. by lm-sensors. |
| 80 | */ |
| 81 | |
| 82 | /* Relevant GPIO register information is available in the |
| 83 | * AMD SP5100 Register Reference Guide rev. 3.03, page 130 |
| 84 | */ |
| 85 | static void switch_spd_mux(uint8_t channel) |
| 86 | { |
| 87 | uint8_t byte; |
| 88 | |
| 89 | byte = pci_read_config8(PCI_DEV(0, 0x14, 0), 0x54); |
| 90 | byte &= ~0xc; /* Clear SPD mux GPIOs */ |
| 91 | byte &= ~0xc0; /* Enable SPD mux GPIO output drivers */ |
| 92 | byte |= (channel << 2) & 0xc; /* Set SPD mux GPIOs */ |
| 93 | pci_write_config8(PCI_DEV(0, 0x14, 0), 0x54, byte); |
| 94 | } |
| 95 | |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 96 | static const uint8_t spd_addr_fam15[] = { |
| 97 | // Socket 0 Node 0 ("Node 0") |
| 98 | RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, |
| 99 | // Socket 0 Node 1 ("Node 1") |
| 100 | RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, |
| 101 | // Socket 1 Node 0 ("Node 2") |
| 102 | RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, |
| 103 | // Socket 1 Node 1 ("Node 3") |
| 104 | RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, |
| 105 | }; |
| 106 | |
| 107 | static const uint8_t spd_addr_fam10[] = { |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 108 | // Socket 0 Node 0 ("Node 0") |
| 109 | RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, |
| 110 | // Socket 0 Node 1 ("Node 1") |
| 111 | RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, |
| 112 | // Socket 1 Node 1 ("Node 2") |
| 113 | RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, |
| 114 | // Socket 1 Node 0 ("Node 3") |
| 115 | RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, |
| 116 | }; |
| 117 | |
| 118 | static void activate_spd_rom(const struct mem_controller *ctrl) { |
| 119 | struct sys_info *sysinfo = &sysinfo_car; |
| 120 | |
| 121 | printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); |
| 122 | if (ctrl->node_id == 0) { |
| 123 | printk(BIOS_DEBUG, "enable_spd_node0()\n"); |
| 124 | switch_spd_mux(0x2); |
| 125 | } else if (ctrl->node_id == 1) { |
| 126 | printk(BIOS_DEBUG, "enable_spd_node1()\n"); |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 127 | switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x2:0x3); |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 128 | } else if (ctrl->node_id == 2) { |
| 129 | printk(BIOS_DEBUG, "enable_spd_node2()\n"); |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 130 | switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x3:0x2); |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 131 | } else if (ctrl->node_id == 3) { |
| 132 | printk(BIOS_DEBUG, "enable_spd_node3()\n"); |
| 133 | switch_spd_mux(0x3); |
| 134 | } |
| 135 | } |
| 136 | |
| 137 | /* Voltages are specified by index |
| 138 | * Valid indicies for this platform are: |
| 139 | * 0: 1.5V |
| 140 | * 1: 1.35V |
| 141 | * 2: 1.25V |
| 142 | * 3: 1.15V |
| 143 | */ |
| 144 | static void set_ddr3_voltage(uint8_t node, uint8_t index) { |
| 145 | uint8_t byte; |
Timothy Pearson | 502d457 | 2015-05-10 04:37:56 -0500 | [diff] [blame] | 146 | uint8_t value = 0; |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 147 | |
| 148 | if (index == 0) |
| 149 | value = 0x0; |
| 150 | else if (index == 1) |
| 151 | value = 0x1; |
| 152 | else if (index == 2) |
| 153 | value = 0x4; |
| 154 | else if (index == 3) |
| 155 | value = 0x5; |
| 156 | if (node == 1) |
| 157 | value <<= 1; |
| 158 | |
| 159 | /* Set GPIOs */ |
| 160 | byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0xd1); |
| 161 | if (node == 0) |
| 162 | byte &= ~0x5; |
| 163 | if (node == 1) |
| 164 | byte &= ~0xa; |
| 165 | byte |= value; |
| 166 | pci_write_config8(PCI_DEV(0, 0x14, 3), 0xd1, byte); |
| 167 | |
| 168 | /* Enable GPIO output drivers */ |
| 169 | byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0xd0); |
| 170 | byte &= 0x0f; |
| 171 | pci_write_config8(PCI_DEV(0, 0x14, 3), 0xd0, byte); |
Timothy Pearson | 502d457 | 2015-05-10 04:37:56 -0500 | [diff] [blame] | 172 | |
| 173 | printk(BIOS_DEBUG, "Node %02d DIMM voltage set to index %02x\n", node, index); |
| 174 | } |
| 175 | |
| 176 | void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, |
| 177 | struct DCTStatStruc *pDCTstatA) { |
| 178 | /* This mainboard allows the DIMM voltage to be set per-socket. |
| 179 | * Therefore, for each socket, iterate over all DIMMs to find the |
| 180 | * lowest supported voltage common to all DIMMs on that socket. |
| 181 | */ |
| 182 | uint8_t nvram; |
| 183 | uint8_t dimm; |
| 184 | uint8_t node; |
| 185 | uint8_t socket; |
| 186 | uint8_t allowed_voltages = 0xf; /* The mainboard VRMs allow 1.15V, 1.25V, 1.35V, and 1.5V */ |
Felix Held | 69e89f2 | 2015-11-10 01:00:47 +0100 | [diff] [blame] | 187 | uint8_t socket_allowed_voltages = allowed_voltages; |
Timothy Pearson | 502d457 | 2015-05-10 04:37:56 -0500 | [diff] [blame] | 188 | uint32_t set_voltage = 0; |
| 189 | |
| 190 | if (get_option(&nvram, "minimum_memory_voltage") == CB_SUCCESS) { |
| 191 | switch (nvram) { |
| 192 | case 2: |
| 193 | allowed_voltages = 0x7; /* Allow 1.25V, 1.35V, and 1.5V */ |
| 194 | break; |
| 195 | case 1: |
| 196 | allowed_voltages = 0x3; /* Allow 1.35V and 1.5V */ |
| 197 | break; |
| 198 | case 0: |
| 199 | default: |
| 200 | allowed_voltages = 0x1; /* Allow 1.5V only */ |
| 201 | break; |
| 202 | } |
| 203 | } |
| 204 | |
| 205 | for (node = 0; node < MAX_NODES_SUPPORTED; node++) { |
| 206 | socket = node / 2; |
Timothy Pearson | 502d457 | 2015-05-10 04:37:56 -0500 | [diff] [blame] | 207 | struct DCTStatStruc *pDCTstat; |
| 208 | pDCTstat = pDCTstatA + node; |
Felix Held | 69e89f2 | 2015-11-10 01:00:47 +0100 | [diff] [blame] | 209 | |
| 210 | /* reset socket_allowed_voltages before processing each socket */ |
| 211 | if (!(node % 2)) |
| 212 | socket_allowed_voltages = allowed_voltages; |
| 213 | |
Timothy Pearson | 502d457 | 2015-05-10 04:37:56 -0500 | [diff] [blame] | 214 | if (pDCTstat->NodePresent) { |
| 215 | for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { |
| 216 | if (pDCTstat->DIMMValid & (1 << dimm)) { |
Felix Held | 69e89f2 | 2015-11-10 01:00:47 +0100 | [diff] [blame] | 217 | socket_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm]; |
Timothy Pearson | 502d457 | 2015-05-10 04:37:56 -0500 | [diff] [blame] | 218 | } |
| 219 | } |
| 220 | } |
| 221 | |
Felix Held | 69e89f2 | 2015-11-10 01:00:47 +0100 | [diff] [blame] | 222 | /* set voltage per socket after processing last contained node */ |
Timothy Pearson | 502d457 | 2015-05-10 04:37:56 -0500 | [diff] [blame] | 223 | if (pDCTstat->NodePresent && (node % 2)) { |
| 224 | /* Set voltages */ |
Felix Held | 69e89f2 | 2015-11-10 01:00:47 +0100 | [diff] [blame] | 225 | if (socket_allowed_voltages & 0x8) { |
Timothy Pearson | e619a9a | 2015-09-05 19:37:57 -0500 | [diff] [blame] | 226 | set_voltage = 0x8; |
Timothy Pearson | 502d457 | 2015-05-10 04:37:56 -0500 | [diff] [blame] | 227 | set_ddr3_voltage(socket, 3); |
Felix Held | 69e89f2 | 2015-11-10 01:00:47 +0100 | [diff] [blame] | 228 | } else if (socket_allowed_voltages & 0x4) { |
Timothy Pearson | e619a9a | 2015-09-05 19:37:57 -0500 | [diff] [blame] | 229 | set_voltage = 0x4; |
Timothy Pearson | 502d457 | 2015-05-10 04:37:56 -0500 | [diff] [blame] | 230 | set_ddr3_voltage(socket, 2); |
Felix Held | 69e89f2 | 2015-11-10 01:00:47 +0100 | [diff] [blame] | 231 | } else if (socket_allowed_voltages & 0x2) { |
Timothy Pearson | e619a9a | 2015-09-05 19:37:57 -0500 | [diff] [blame] | 232 | set_voltage = 0x2; |
Timothy Pearson | 502d457 | 2015-05-10 04:37:56 -0500 | [diff] [blame] | 233 | set_ddr3_voltage(socket, 1); |
| 234 | } else { |
Timothy Pearson | e619a9a | 2015-09-05 19:37:57 -0500 | [diff] [blame] | 235 | set_voltage = 0x1; |
Timothy Pearson | 502d457 | 2015-05-10 04:37:56 -0500 | [diff] [blame] | 236 | set_ddr3_voltage(socket, 0); |
| 237 | } |
| 238 | |
Timothy Pearson | e619a9a | 2015-09-05 19:37:57 -0500 | [diff] [blame] | 239 | /* Save final DIMM voltages for MCT and SMBIOS use */ |
Timothy Pearson | 502d457 | 2015-05-10 04:37:56 -0500 | [diff] [blame] | 240 | if (pDCTstat->NodePresent) { |
| 241 | for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { |
| 242 | pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage; |
| 243 | } |
| 244 | } |
| 245 | pDCTstat = pDCTstatA + (node - 1); |
| 246 | if (pDCTstat->NodePresent) { |
| 247 | for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { |
| 248 | pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage; |
| 249 | } |
| 250 | } |
| 251 | } |
| 252 | } |
Timothy Pearson | e619a9a | 2015-09-05 19:37:57 -0500 | [diff] [blame] | 253 | |
| 254 | /* Allow the DDR supply voltages to settle */ |
| 255 | udelay(100000); |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 256 | } |
| 257 | |
| 258 | static void set_peripheral_control_lines(void) { |
| 259 | uint8_t byte; |
Timothy Pearson | 919d9ba | 2015-08-11 18:38:06 -0500 | [diff] [blame] | 260 | uint8_t nvram; |
| 261 | uint8_t enable_ieee1394; |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 262 | |
Timothy Pearson | 919d9ba | 2015-08-11 18:38:06 -0500 | [diff] [blame] | 263 | enable_ieee1394 = 1; |
| 264 | |
| 265 | if (get_option(&nvram, "ieee1394_controller") == CB_SUCCESS) |
| 266 | enable_ieee1394 = nvram & 0x1; |
| 267 | |
| 268 | if (enable_ieee1394) { |
| 269 | /* Enable PCICLK5 (onboard FireWire device) */ |
| 270 | outb(0x41, 0xcd6); |
| 271 | outb(0x02, 0xcd7); |
| 272 | } else { |
| 273 | /* Disable PCICLK5 (onboard FireWire device) */ |
| 274 | outb(0x41, 0xcd6); |
| 275 | outb(0x00, 0xcd7); |
| 276 | } |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 277 | |
| 278 | /* Enable the RTC AltCentury register */ |
| 279 | outb(0x41, 0xcd6); |
| 280 | byte = inb(0xcd7); |
| 281 | byte |= 0x10; |
| 282 | outb(byte, 0xcd7); |
| 283 | } |
| 284 | |
| 285 | #ifdef TEST_MEMORY |
| 286 | static void execute_memory_test(void) |
| 287 | { |
| 288 | /* Test DRAM functionality */ |
| 289 | uint32_t i; |
| 290 | uint32_t* dataptr; |
| 291 | printk(BIOS_DEBUG, "Writing test patterns to memory...\n"); |
| 292 | for (i=0; i < 0x1000000; i = i + 8) { |
| 293 | dataptr = (void *)(0x300000 + i); |
| 294 | *dataptr = 0x55555555; |
| 295 | dataptr = (void *)(0x300000 + i + 4); |
| 296 | *dataptr = 0xaaaaaaaa; |
| 297 | } |
| 298 | printk(BIOS_DEBUG, "Done!\n"); |
| 299 | printk(BIOS_DEBUG, "Testing memory...\n"); |
| 300 | uint32_t readback; |
| 301 | for (i=0; i < 0x1000000; i = i + 8) { |
| 302 | dataptr = (void *)(0x300000 + i); |
| 303 | readback = *dataptr; |
| 304 | if (readback != 0x55555555) |
| 305 | printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, 0x55555555); |
| 306 | dataptr = (void *)(0x300000 + i + 4); |
| 307 | readback = *dataptr; |
| 308 | if (readback != 0xaaaaaaaa) |
| 309 | printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, 0xaaaaaaaa); |
| 310 | } |
| 311 | printk(BIOS_DEBUG, "Done!\n"); |
| 312 | } |
| 313 | #endif |
| 314 | |
Timothy Pearson | ecd4cfc | 2015-11-05 13:16:55 -0600 | [diff] [blame] | 315 | static spinlock_t printk_spinlock CAR_GLOBAL; |
| 316 | |
| 317 | spinlock_t* romstage_console_lock(void) |
| 318 | { |
| 319 | return car_get_var_ptr(&printk_spinlock); |
| 320 | } |
| 321 | |
| 322 | void initialize_romstage_console_lock(void) |
| 323 | { |
| 324 | car_get_var(printk_spinlock) = SPIN_LOCK_UNLOCKED; |
| 325 | } |
| 326 | |
Timothy Pearson | 5f2bf6d | 2015-08-28 20:02:45 -0500 | [diff] [blame] | 327 | static spinlock_t nvram_cbfs_spinlock CAR_GLOBAL; |
| 328 | |
| 329 | spinlock_t* romstage_nvram_cbfs_lock(void) |
| 330 | { |
| 331 | return car_get_var_ptr(&nvram_cbfs_spinlock); |
| 332 | } |
| 333 | |
| 334 | void initialize_romstage_nvram_cbfs_lock(void) |
| 335 | { |
| 336 | car_get_var(nvram_cbfs_spinlock) = SPIN_LOCK_UNLOCKED; |
| 337 | } |
| 338 | |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 339 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 340 | { |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 341 | uint32_t esp; |
| 342 | __asm__ volatile ( |
| 343 | "movl %%esp, %0" |
| 344 | : "=r" (esp) |
| 345 | ); |
| 346 | |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 347 | struct sys_info *sysinfo = &sysinfo_car; |
| 348 | |
Timothy Pearson | b4b298c | 2015-09-03 17:39:51 -0500 | [diff] [blame] | 349 | /* Limit the maximum HT speed to 2.6GHz to prevent lockups |
| 350 | * due to HT CPU <--> CPU wiring not being validated to 3.2GHz |
| 351 | */ |
| 352 | sysinfo->ht_link_cfg.ht_speed_limit = 2600; |
| 353 | |
Timothy Pearson | babb2e6 | 2015-05-07 01:32:08 -0500 | [diff] [blame] | 354 | uint32_t bsp_apicid = 0, val; |
| 355 | uint8_t byte; |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 356 | msr_t msr; |
| 357 | |
Timothy Pearson | babb2e6 | 2015-05-07 01:32:08 -0500 | [diff] [blame] | 358 | int s3resume = acpi_is_wakeup_s3(); |
| 359 | |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 360 | if (!cpu_init_detectedx && boot_cpu()) { |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 361 | /* Initial timestamp */ |
| 362 | timestamp_init(timestamp_get()); |
| 363 | timestamp_add_now(TS_START_ROMSTAGE); |
| 364 | |
Timothy Pearson | 5f2bf6d | 2015-08-28 20:02:45 -0500 | [diff] [blame] | 365 | /* Initialize the printk and nvram CBFS spinlocks */ |
Timothy Pearson | ecd4cfc | 2015-11-05 13:16:55 -0600 | [diff] [blame] | 366 | initialize_romstage_console_lock(); |
Timothy Pearson | 5f2bf6d | 2015-08-28 20:02:45 -0500 | [diff] [blame] | 367 | initialize_romstage_nvram_cbfs_lock(); |
Timothy Pearson | ecd4cfc | 2015-11-05 13:16:55 -0600 | [diff] [blame] | 368 | |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 369 | /* Nothing special needs to be done to find bus 0 */ |
| 370 | /* Allow the HT devices to be found */ |
| 371 | set_bsp_node_CHtExtNodeCfgEn(); |
| 372 | enumerate_ht_chain(); |
| 373 | |
| 374 | /* SR56x0 pcie bridges block pci_locate_device() before pcie training. |
| 375 | * disable all pcie bridges on SR56x0 to work around it |
| 376 | */ |
| 377 | sr5650_disable_pcie_bridge(); |
| 378 | |
| 379 | /* Initialize southbridge */ |
| 380 | sb7xx_51xx_pci_port80(); |
| 381 | |
| 382 | /* Initialize early serial */ |
| 383 | nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 384 | console_init(); |
Timothy Pearson | babb2e6 | 2015-05-07 01:32:08 -0500 | [diff] [blame] | 385 | |
| 386 | /* Disable LPC legacy DMA support to prevent lockup */ |
| 387 | byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0x78); |
| 388 | byte &= ~(1 << 0); |
| 389 | pci_write_config8(PCI_DEV(0, 0x14, 3), 0x78, byte); |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 390 | } |
| 391 | |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 392 | printk(BIOS_SPEW, "Initial stack pointer: %08x\n", esp); |
| 393 | |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 394 | post_code(0x30); |
| 395 | |
| 396 | if (bist == 0) |
| 397 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
| 398 | |
| 399 | post_code(0x32); |
| 400 | |
| 401 | enable_sr5650_dev8(); |
| 402 | sb7xx_51xx_lpc_init(); |
| 403 | |
| 404 | if (CONFIG_MAX_PHYSICAL_CPUS != 4) |
| 405 | printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket AMD G34 board!\n", CONFIG_MAX_PHYSICAL_CPUS); |
| 406 | |
| 407 | /* Halt if there was a built in self test failure */ |
| 408 | report_bist_failure(bist); |
| 409 | |
| 410 | val = cpuid_eax(1); |
| 411 | printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); |
| 412 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
| 413 | printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); |
| 414 | printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); |
| 415 | |
| 416 | /* Setup sysinfo defaults */ |
| 417 | set_sysinfo_in_ram(0); |
| 418 | |
| 419 | update_microcode(val); |
| 420 | |
| 421 | post_code(0x33); |
| 422 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 423 | cpuSetAMDMSR(0); |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 424 | post_code(0x34); |
| 425 | |
| 426 | amd_ht_init(sysinfo); |
| 427 | amd_ht_fixup(sysinfo); |
| 428 | post_code(0x35); |
| 429 | |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 430 | /* Setup nodes PCI space and start core 0 AP init. */ |
| 431 | finalize_node_setup(sysinfo); |
| 432 | |
| 433 | /* Setup any mainboard PCI settings etc. */ |
| 434 | setup_mb_resource_map(); |
| 435 | post_code(0x36); |
| 436 | |
Timothy Pearson | e619a9a | 2015-09-05 19:37:57 -0500 | [diff] [blame] | 437 | /* Wait for all the APs core0 started by finalize_node_setup. */ |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 438 | wait_all_core0_started(); |
| 439 | |
| 440 | /* run _early_setup before soft-reset. */ |
| 441 | sr5650_early_setup(); |
| 442 | sb7xx_51xx_early_setup(); |
| 443 | |
Timothy Pearson | e619a9a | 2015-09-05 19:37:57 -0500 | [diff] [blame] | 444 | if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { |
| 445 | /* Core0 on each node is configured. Now setup any additional cores. */ |
| 446 | printk(BIOS_DEBUG, "start_other_cores()\n"); |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 447 | start_other_cores(bsp_apicid); |
Timothy Pearson | e619a9a | 2015-09-05 19:37:57 -0500 | [diff] [blame] | 448 | post_code(0x37); |
| 449 | wait_all_other_cores_started(bsp_apicid); |
| 450 | } |
| 451 | |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 452 | if (IS_ENABLED(CONFIG_SET_FIDVID)) { |
| 453 | msr = rdmsr(0xc0010071); |
| 454 | printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); |
| 455 | |
| 456 | /* FIXME: The sb fid change may survive the warm reset and only need to be done once */ |
| 457 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 458 | |
| 459 | post_code(0x39); |
| 460 | |
Timothy Pearson | e619a9a | 2015-09-05 19:37:57 -0500 | [diff] [blame] | 461 | #if IS_ENABLED(CONFIG_SET_FIDVID) |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 462 | if (!warm_reset_detect(0)) { // BSP is node 0 |
| 463 | init_fidvid_bsp(bsp_apicid, sysinfo->nodes); |
| 464 | } else { |
| 465 | init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 |
| 466 | } |
Timothy Pearson | e619a9a | 2015-09-05 19:37:57 -0500 | [diff] [blame] | 467 | #endif |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 468 | |
| 469 | post_code(0x3A); |
| 470 | |
| 471 | /* show final fid and vid */ |
| 472 | msr=rdmsr(0xc0010071); |
| 473 | printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); |
| 474 | } |
| 475 | |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 476 | post_code(0x38); |
| 477 | |
| 478 | init_timer(); // Need to use TMICT to synconize FID/VID |
| 479 | |
| 480 | sr5650_htinit(); |
| 481 | |
Timothy Pearson | e619a9a | 2015-09-05 19:37:57 -0500 | [diff] [blame] | 482 | /* Reset for HT, FIDVID, PLL and errata changes to take effect. */ |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 483 | if (!warm_reset_detect(0)) { |
| 484 | printk(BIOS_INFO, "...WARM RESET...\n\n\n"); |
| 485 | soft_reset(); |
| 486 | die("After soft_reset_x - shouldn't see this message!!!\n"); |
| 487 | } |
| 488 | |
Timothy Pearson | 2595496 | 2015-11-24 04:06:10 -0600 | [diff] [blame] | 489 | sr5650_htinit_dect_and_enable_isochronous_link(); |
| 490 | |
Timothy Pearson | 502d457 | 2015-05-10 04:37:56 -0500 | [diff] [blame] | 491 | /* Set default DDR memory voltage |
| 492 | * This will be overridden later during RAM initialization |
Timothy Pearson | babb2e6 | 2015-05-07 01:32:08 -0500 | [diff] [blame] | 493 | */ |
| 494 | set_lpc_sticky_ctl(1); /* Retain LPC/IMC GPIO configuration during S3 sleep */ |
| 495 | if (!s3resume) { /* Avoid supply voltage glitches while the DIMMs are retaining data */ |
| 496 | set_ddr3_voltage(0, 0); /* Node 0 */ |
| 497 | set_ddr3_voltage(1, 0); /* Node 1 */ |
| 498 | } |
| 499 | |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 500 | /* Set up peripheral control lines */ |
| 501 | set_peripheral_control_lines(); |
| 502 | |
| 503 | post_code(0x3B); |
| 504 | |
| 505 | /* It's the time to set ctrl in sysinfo now; */ |
| 506 | printk(BIOS_DEBUG, "fill_mem_ctrl() detected %d nodes\n", sysinfo->nodes); |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 507 | if (is_fam15h()) |
| 508 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam15); |
| 509 | else |
| 510 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam10); |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 511 | post_code(0x3D); |
| 512 | |
| 513 | #if 0 |
| 514 | /* FIXME |
| 515 | * After the AMD K10 code has been converted to use |
| 516 | * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block |
| 517 | */ |
| 518 | if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) { |
| 519 | dump_spd_registers(&cpu[0]); |
| 520 | dump_smbus_registers(); |
| 521 | } |
| 522 | #endif |
| 523 | |
| 524 | post_code(0x40); |
| 525 | |
| 526 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 527 | printk(BIOS_DEBUG, "raminit_amdmct()\n"); |
| 528 | raminit_amdmct(sysinfo); |
| 529 | timestamp_add_now(TS_AFTER_INITRAM); |
| 530 | |
| 531 | #if !IS_ENABLED(CONFIG_LATE_CBMEM_INIT) |
Timothy Pearson | babb2e6 | 2015-05-07 01:32:08 -0500 | [diff] [blame] | 532 | if (s3resume) |
| 533 | cbmem_initialize(); |
| 534 | else |
| 535 | cbmem_initialize_empty(); |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 536 | post_code(0x41); |
| 537 | |
| 538 | amdmct_cbmem_store_info(sysinfo); |
| 539 | #endif |
| 540 | |
| 541 | printk(BIOS_DEBUG, "disable_spd()\n"); |
| 542 | switch_spd_mux(0x1); |
| 543 | |
| 544 | sr5650_before_pci_init(); |
| 545 | sb7xx_51xx_before_pci_init(); |
| 546 | |
| 547 | /* Configure SP5100 GPIOs to match vendor settings */ |
| 548 | pci_write_config16(PCI_DEV(0, 0x14, 0), 0x50, 0x0170); |
| 549 | pci_write_config16(PCI_DEV(0, 0x14, 0), 0x54, 0x0707); |
| 550 | pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0); |
| 551 | pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0); |
| 552 | |
| 553 | timestamp_add_now(TS_END_ROMSTAGE); |
| 554 | |
| 555 | #ifdef TEST_MEMORY |
| 556 | execute_memory_test(); |
| 557 | #endif |
| 558 | |
| 559 | post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. |
| 560 | post_code(0x43); // Should never see this post code. |
| 561 | } |
| 562 | |
| 563 | /** |
| 564 | * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) |
| 565 | * Description: |
| 566 | * This routine is called every time a non-coherent chain is processed. |
| 567 | * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a |
| 568 | * swap list. The first part of the list controls the BUID assignment and the |
| 569 | * second part of the list provides the device to device linking. Device orientation |
| 570 | * can be detected automatically, or explicitly. See documentation for more details. |
| 571 | * |
| 572 | * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially |
| 573 | * based on each device's unit count. |
| 574 | * |
| 575 | * Parameters: |
| 576 | * @param[in] node = The node on which this chain is located |
| 577 | * @param[in] link = The link on the host for this chain |
| 578 | * @param[out] List = supply a pointer to a list |
| 579 | */ |
| 580 | BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) |
| 581 | { |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 582 | /* Force BUID to 0 */ |
| 583 | static const u8 swaplist[] = {0, 0, 0xFF, 0, 0xFF}; |
Timothy Pearson | 48bfcdf | 2015-08-02 21:28:31 -0500 | [diff] [blame] | 584 | if ((is_fam15h() && (node == 0) && (link == 1)) /* Family 15h BSP SB link */ |
| 585 | || (!is_fam15h() && (node == 0) && (link == 3))) { /* Family 10h BSP SB link */ |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 586 | *List = swaplist; |
| 587 | return 1; |
| 588 | } |
| 589 | |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 590 | return 0; |
Timothy Pearson | 919d9ba | 2015-08-11 18:38:06 -0500 | [diff] [blame] | 591 | } |