Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
| 5 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <arch/io.h> |
| 21 | #include <cpu/x86/msr.h> |
| 22 | #include <cpu/amd/mtrr.h> |
| 23 | #include <device/pci_def.h> |
| 24 | #include <southbridge/amd/sb700/sb700.h> |
| 25 | #include <southbridge/amd/sr5650/cmn.h> |
| 26 | |
| 27 | |
| 28 | void set_pcie_reset(void); |
| 29 | void set_pcie_dereset(void); |
| 30 | |
| 31 | void set_pcie_reset(void) |
| 32 | { |
| 33 | device_t pcie_core_dev; |
| 34 | |
| 35 | pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); |
| 36 | set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828); |
| 37 | set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028); |
| 38 | } |
| 39 | |
| 40 | void set_pcie_dereset(void) |
| 41 | { |
| 42 | device_t pcie_core_dev; |
| 43 | |
| 44 | pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); |
| 45 | set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F); |
| 46 | set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F); |
| 47 | } |
| 48 | |
| 49 | /************************************************* |
| 50 | * enable the dedicated function in kgpe-d16 board. |
| 51 | * This function is called earlier than sr5650_enable. |
| 52 | *************************************************/ |
| 53 | static void mainboard_enable(device_t dev) |
| 54 | { |
| 55 | printk(BIOS_INFO, "Mainboard KGPE-D16 Enable. dev=0x%p\n", dev); |
| 56 | |
| 57 | msr_t msr, msr2; |
| 58 | |
| 59 | /* TOP_MEM: the top of DRAM below 4G */ |
| 60 | msr = rdmsr(TOP_MEM); |
| 61 | printk |
| 62 | (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", |
| 63 | __func__, msr.lo, msr.hi); |
| 64 | |
| 65 | /* TOP_MEM2: the top of DRAM above 4G */ |
| 66 | msr2 = rdmsr(TOP_MEM2); |
| 67 | printk |
| 68 | (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", |
| 69 | __func__, msr2.lo, msr2.hi); |
| 70 | |
| 71 | set_pcie_dereset(); |
| 72 | /* get_ide_dma66(); */ |
| 73 | } |
| 74 | |
Timothy Pearson | 2b20677 | 2015-06-09 18:57:23 -0500 | [diff] [blame] | 75 | /* override the default SATA PHY setup */ |
| 76 | void sb7xx_51xx_setup_sata_phys(struct device *dev) |
| 77 | { |
| 78 | /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */ |
| 79 | pci_write_config16(dev, 0x86, 0x2c00); |
| 80 | |
| 81 | /* RPR7.6.2 SATA GENI PHY ports setting */ |
| 82 | pci_write_config32(dev, 0x88, 0x01b48016); |
| 83 | pci_write_config32(dev, 0x8c, 0x01b48016); |
| 84 | pci_write_config32(dev, 0x90, 0x01b48016); |
| 85 | pci_write_config32(dev, 0x94, 0x01b48016); |
| 86 | pci_write_config32(dev, 0x98, 0x01b48016); |
| 87 | pci_write_config32(dev, 0x9c, 0x01b48016); |
| 88 | |
| 89 | /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */ |
| 90 | pci_write_config16(dev, 0xa0, 0xa07a); |
| 91 | pci_write_config16(dev, 0xa2, 0xa07a); |
| 92 | pci_write_config16(dev, 0xa4, 0xa07a); |
| 93 | pci_write_config16(dev, 0xa6, 0xa07a); |
| 94 | pci_write_config16(dev, 0xa8, 0xa07a); |
| 95 | pci_write_config16(dev, 0xaa, 0xa07a); |
| 96 | } |
| 97 | |
Timothy Pearson | f89a05e | 2015-06-09 19:34:16 -0500 | [diff] [blame] | 98 | /* override the default SATA port setup */ |
| 99 | void sb7xx_51xx_setup_sata_port_indication(void *sata_bar5) |
| 100 | { |
| 101 | uint32_t dword; |
| 102 | |
| 103 | /* RPR7.9 Program Port Indication Registers */ |
| 104 | dword = read32(sata_bar5 + 0xf8); |
| 105 | dword &= ~(0x3f << 12); /* All ports are iSATA */ |
| 106 | dword &= ~0x3f; |
| 107 | write32(sata_bar5 + 0xf8, dword); |
| 108 | |
| 109 | dword = read32(sata_bar5 + 0xfc); |
| 110 | dword &= ~(0x1 << 20); /* No eSATA ports are present */ |
| 111 | write32(sata_bar5 + 0xfc, dword); |
| 112 | } |
| 113 | |
Timothy Pearson | 53538be | 2015-04-30 01:47:31 -0500 | [diff] [blame] | 114 | struct chip_operations mainboard_ops = { |
| 115 | .enable_dev = mainboard_enable, |
| 116 | }; |