| Timothy Pearson | ab95702 | 2015-10-28 02:59:40 -0500 | [diff] [blame] | 1 | ==================================================================================================== |
| 2 | SPD mux |
| 3 | ==================================================================================================== |
| 4 | |
| 5 | DIMM_A1 SDA signal traced to U6 pin 1 |
| 6 | Destructive testing of failed board (removal of U7 northbridge!) yielded the following information: |
| 7 | U6 S0 <--> U7 W2 |
| 8 | U6 S1 <--> U7 W3 |
| 9 | |
| 10 | Proprietary BIOS enables the SPD during POST with: |
| 11 | S0: LOW |
| 12 | S1: LOW |
| 13 | |
| 14 | then temporarily switches to: |
| 15 | S0: LOW |
| 16 | S1: HIGH |
| 17 | |
| 18 | then switches to runtime mode with: |
| 19 | S0: HIGH |
| 20 | S1: LOW |
| 21 | |
| 22 | After probing with a custom GPIO-flipping tool under Linux the following GPIO mappings were found: |
| 23 | CK804 pin W2 <--> GPIO43 |
| 24 | CK804 pin W3 <--> GPIO44 |
| 25 | |
| 26 | ==================================================================================================== |
| 27 | W83793 (U46) |
| 28 | ==================================================================================================== |
| 29 | |
| 30 | Sensor mappings: |
| 31 | FRNT_FAN1: FAN3 |
| 32 | FRNT_FAN2: FAN4 |
| 33 | FRNT_FAN3: FAN5 |
| 34 | FRNT_FAN4: FAN6 |
| 35 | FRNT_FAN5: FAN9 |
| 36 | FRNT_FAN6: FAN10 |
| 37 | REAR_FAN1: FAN7 |
| 38 | REAR_FAN2: FAN8 |
| 39 | REAR_FAN3: FAN11 |
| 40 | REAR_FAN4: FAN12 |
| 41 | |
| 42 | ==================================================================================================== |
| 43 | Other hardware |
| 44 | ==================================================================================================== |
| 45 | |
| 46 | Power LED (-) is connected to U15 (SuperIO) pin 64 via U4 pins 5,6 and a small MOSFET |
| 47 | ID LED (-) is connected to a ??? via U4 pins 1,2,3,4 and U77 pins 5,6 |
| 48 | It appears that setting U15 (SuperIO) pin 88 LOW will override the ID LED and force it ON |
| 49 | |
| 50 | RECOVERY2 middle pin is connected to U15 (SuperIO) pin 89 |
| 51 | Normal is HIGH, recovery is LOW. |
| 52 | |
| 53 | PCIe slot WAKE# connects to U7 pin E23 (PCIE_WAKE#) |
| 54 | |
| 55 | CPU_WARN1 is driven by (???) via a simple buffer (U13 pin 10) |
| 56 | MEM_WARN1 is driven by U7 pin AD3 (CPUVDD_EN) via a simple buffer (U101 pin 3) |
| 57 | |
| 58 | U7 pin AK3 is disconnected (routed to unpopulated capacitor/resistor) |
| 59 | PU1 pin 37 (VDDPWRGD) drives U7 pin AJ4 (CPU_VLD) |
| 60 | A small MOSFET directly above another small MOSFET directly above the right-hand edge of the PCIe slot drives U7 pin AK5 (HT_VLD) |
| 61 | |
| 62 | When > Barcelona CPU installed on PCB rev 1.04G: |
| 63 | U7 pin AK4 (MEM_VLD): HIGH |
| 64 | PU1 pin 37: LOW |
| 65 | U7 pin AK5: LOW |
| 66 | |
| 67 | HyperTransport 1.2V supply appears to be generated by a linear regulator containing Q191 and downconverting the CK804 1.5V supply |
| 68 | The enable pin appears to be tied to AUX_PANEL pin 1 (+5VSB) via a resistor |
| 69 | Through two MOSFETs the HT supply enable pin is tied to U7 pin AE3 (HTVDD_EN) |