Timothy Pearson | ab95702 | 2015-10-28 02:59:40 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
| 5 | * |
| 6 | * Copyright (C) 2007 AMD |
| 7 | * Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
Timothy Pearson | ab95702 | 2015-10-28 02:59:40 -0500 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | unsigned int get_sbdn(unsigned bus); |
| 21 | |
| 22 | #include <stdint.h> |
| 23 | #include <string.h> |
| 24 | #include <device/pci_def.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <arch/io.h> |
| 27 | #include <device/pnp_def.h> |
| 28 | #include <pc80/mc146818rtc.h> |
| 29 | #include <console/console.h> |
| 30 | #include <timestamp.h> |
| 31 | #include <cpu/amd/model_fxx_rev.h> |
| 32 | #include "southbridge/nvidia/ck804/early_smbus.h" |
| 33 | #include <reset.h> |
| 34 | #include <northbridge/amd/amdk8/raminit.h> |
| 35 | #include "northbridge/amd/amdk8/reset_test.c" |
| 36 | #include <cpu/x86/bist.h> |
| 37 | #include <delay.h> |
| 38 | #include "northbridge/amd/amdk8/debug.c" |
| 39 | #include <cpu/amd/mtrr.h> |
| 40 | #include <superio/winbond/common/winbond.h> |
| 41 | #include <superio/winbond/w83627thg/w83627thg.h> |
| 42 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
| 43 | |
| 44 | #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) |
| 45 | |
| 46 | static void memreset(int controllers, const struct mem_controller *ctrl) { } |
| 47 | |
| 48 | static void activate_spd_rom(const struct mem_controller *ctrl); |
| 49 | |
| 50 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 51 | { |
| 52 | return smbus_read_byte(device, address); |
| 53 | } |
| 54 | |
| 55 | #include <northbridge/amd/amdk8/amdk8.h> |
| 56 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
| 57 | #include "northbridge/amd/amdk8/coherent_ht.c" |
| 58 | #include "northbridge/amd/amdk8/raminit_f.c" |
| 59 | #include "lib/generic_sdram.c" |
| 60 | #include "resourcemap.c" |
| 61 | #include "cpu/amd/dualcore/dualcore.c" |
| 62 | #include <spd.h> |
| 63 | #include "cpu/amd/model_fxx/init_cpus.c" |
| 64 | #include "cpu/amd/model_fxx/fidvid.c" |
Timothy Pearson | 74b13a5 | 2015-10-31 15:00:23 -0500 | [diff] [blame] | 65 | #include "northbridge/amd/amdk8/early_ht.c" |
Timothy Pearson | ab95702 | 2015-10-28 02:59:40 -0500 | [diff] [blame] | 66 | |
| 67 | #define CK804_MB_SETUP \ |
| 68 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/ |
| 69 | |
| 70 | #include <southbridge/nvidia/ck804/early_setup_ss.h> |
| 71 | #include "southbridge/nvidia/ck804/early_setup_car.c" |
| 72 | #include <cpu/amd/microcode.h> |
| 73 | |
| 74 | #define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3) |
| 75 | |
| 76 | /** |
| 77 | * @brief Get SouthBridge device number |
| 78 | * @param[in] bus target bus number |
| 79 | * @return southbridge device number |
| 80 | */ |
| 81 | unsigned int get_sbdn(unsigned bus) |
| 82 | { |
| 83 | device_t dev; |
| 84 | |
| 85 | dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, |
| 86 | PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus); |
| 87 | return (dev >> 15) & 0x1f; |
| 88 | } |
| 89 | |
| 90 | /* |
| 91 | * ASUS KFSN4-DRE specific SPD enable/disable magic. |
| 92 | * |
| 93 | * Setting CK804 GPIO43 and GPIO44 to 0 and 0 respectively will make the |
| 94 | * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD |
| 95 | * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which |
| 96 | * will make RAM init fail. |
| 97 | * |
| 98 | * Disable SPD access after RAM init to allow access to standard SMBus/I2C offsets |
| 99 | * which is required e.g. by lm-sensors. |
| 100 | */ |
| 101 | |
| 102 | #define CK804_BOARD_BOOT_BASE_UNIT_UID 1 |
| 103 | |
| 104 | static const unsigned int ctrl_conf_enable_spd_node0[] = { |
| 105 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/ |
| 106 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/ |
| 107 | }; |
| 108 | |
| 109 | static const unsigned int ctrl_conf_enable_spd_node1[] = { |
| 110 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/ |
| 111 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x01),/* W3,GPIO44, U6 input S1*/ |
| 112 | }; |
| 113 | |
| 114 | static const unsigned int ctrl_conf_disable_spd[] = { |
| 115 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x01),/* W2,GPIO43, U6 input S0*/ |
| 116 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/ |
| 117 | }; |
| 118 | |
| 119 | static const unsigned int ctrl_conf_fix_pci_numbering[] = { |
| 120 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x44), ~(0x00010000), 0x00000000, /* Force CK804 to start its internal device numbering (Base Unit ID) at 0 instead of the power-on default of 1 */ |
| 121 | }; |
| 122 | |
| 123 | static const unsigned int ctrl_conf_enable_msi_mapping[] = { |
| 124 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */ |
| 125 | }; |
| 126 | |
| 127 | static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id) |
| 128 | { |
| 129 | unsigned busn[4], io_base[4]; |
| 130 | int i, ck804_num = 0; |
| 131 | |
| 132 | for (i = 0; i < 4; i++) { |
| 133 | u32 id; |
| 134 | device_t dev; |
| 135 | if (i == 0) /* SB chain */ |
| 136 | dev = PCI_DEV(i * 0x40, bus_unit_id, 0); |
| 137 | else |
| 138 | dev = 0; |
| 139 | id = pci_read_config32(dev, PCI_VENDOR_ID); |
| 140 | if (id == 0x005e10de) { |
| 141 | busn[ck804_num] = i * 0x40; |
| 142 | io_base[ck804_num] = i * 0x4000; |
| 143 | ck804_num++; |
| 144 | } |
| 145 | } |
| 146 | |
| 147 | if (ck804_num < 1) |
| 148 | printk(BIOS_WARNING, "CK804 not found at device base unit id %02x!\n", bus_unit_id); |
| 149 | |
| 150 | ck804_early_set_port(ck804_num, busn, io_base); |
| 151 | |
| 152 | setup_resource_map_x_offset(values, |
| 153 | size, |
| 154 | PCI_DEV(0, bus_unit_id, 0), io_base[0]); |
| 155 | |
| 156 | ck804_early_clear_port(ck804_num, busn, io_base); |
| 157 | } |
| 158 | |
| 159 | static void sio_setup(void) |
| 160 | { |
| 161 | u32 dword; |
| 162 | u8 byte; |
| 163 | |
| 164 | /* Subject decoding */ |
| 165 | byte = pci_read_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b); |
| 166 | byte |= 0x20; |
| 167 | pci_write_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b, byte); |
| 168 | |
| 169 | /* LPC Positive Decode 0 */ |
| 170 | dword = pci_read_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0); |
| 171 | /* Serial 0, Serial 1 */ |
| 172 | dword |= (1 << 0) | (1 << 1); |
| 173 | pci_write_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0, dword); |
| 174 | } |
| 175 | |
| 176 | static const uint16_t spd_addr[] = { |
| 177 | // Node 0 |
| 178 | RC00 | DIMM0, RC00 | DIMM2, RC00 | DIMM4, RC00 | DIMM6, RC00 | DIMM1, RC00 | DIMM3, RC00 | DIMM5, RC00 | DIMM7, |
| 179 | // Node 1 |
| 180 | RC01 | DIMM0, RC01 | DIMM2, RC01 | DIMM4, RC01 | DIMM6, RC01 | DIMM1, RC01 | DIMM3, RC01 | DIMM5, RC01 | DIMM7, |
| 181 | }; |
| 182 | |
| 183 | static void activate_spd_rom(const struct mem_controller *ctrl) { |
| 184 | printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); |
| 185 | if (ctrl->node_id == 0) { |
| 186 | printk(BIOS_DEBUG, "enable_spd_node0()\n"); |
| 187 | ck804_control(ctrl_conf_enable_spd_node0, ARRAY_SIZE(ctrl_conf_enable_spd_node0), CK804_DEVN_BASE); |
| 188 | } |
| 189 | else if (ctrl->node_id == 1) { |
| 190 | printk(BIOS_DEBUG, "enable_spd_node1()\n"); |
| 191 | ck804_control(ctrl_conf_enable_spd_node1, ARRAY_SIZE(ctrl_conf_enable_spd_node1), CK804_DEVN_BASE); |
| 192 | } |
| 193 | } |
| 194 | |
| 195 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 196 | { |
| 197 | struct sys_info *sysinfo = &sysinfo_car; |
| 198 | |
Timothy Pearson | 74b13a5 | 2015-10-31 15:00:23 -0500 | [diff] [blame] | 199 | uint32_t bsp_apicid = 0; |
| 200 | uint32_t dword; |
| 201 | uint8_t needs_reset = 0; |
Timothy Pearson | ab95702 | 2015-10-28 02:59:40 -0500 | [diff] [blame] | 202 | #if IS_ENABLED(CONFIG_SET_FIDVID) |
| 203 | struct cpuid_result cpuid1; |
| 204 | #endif |
| 205 | |
| 206 | timestamp_init(timestamp_get()); |
| 207 | timestamp_add_now(TS_START_ROMSTAGE); |
| 208 | |
Timothy Pearson | 74b13a5 | 2015-10-31 15:00:23 -0500 | [diff] [blame] | 209 | if (!cpu_init_detectedx && boot_cpu()) { |
| 210 | /* Nothing special needs to be done to find bus 0 */ |
| 211 | /* Allow the HT devices to be found */ |
| 212 | enumerate_ht_chain(); |
Timothy Pearson | ab95702 | 2015-10-28 02:59:40 -0500 | [diff] [blame] | 213 | sio_setup(); |
Timothy Pearson | 74b13a5 | 2015-10-31 15:00:23 -0500 | [diff] [blame] | 214 | } |
Timothy Pearson | ab95702 | 2015-10-28 02:59:40 -0500 | [diff] [blame] | 215 | |
| 216 | post_code(0x30); |
| 217 | |
| 218 | if (bist == 0) |
| 219 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
| 220 | |
| 221 | post_code(0x32); |
| 222 | |
| 223 | winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 224 | console_init(); |
| 225 | |
| 226 | if (CONFIG_MAX_PHYSICAL_CPUS != 2) |
| 227 | printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket board!\n", CONFIG_MAX_PHYSICAL_CPUS); |
| 228 | |
| 229 | /* Halt if there was a built in self test failure */ |
| 230 | report_bist_failure(bist); |
| 231 | |
Timothy Pearson | 74b13a5 | 2015-10-31 15:00:23 -0500 | [diff] [blame] | 232 | dword = cpuid_eax(1); |
| 233 | printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", dword); |
Timothy Pearson | ab95702 | 2015-10-28 02:59:40 -0500 | [diff] [blame] | 234 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
| 235 | printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); |
| 236 | printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); |
| 237 | |
| 238 | /* Setup sysinfo defaults */ |
| 239 | set_sysinfo_in_ram(0); |
| 240 | |
| 241 | post_code(0x33); |
| 242 | |
| 243 | setup_coherent_ht_domain(); |
| 244 | post_code(0x35); |
| 245 | |
Timothy Pearson | ab95702 | 2015-10-28 02:59:40 -0500 | [diff] [blame] | 246 | /* Wait for all base cores to start */ |
| 247 | wait_all_core0_started(); |
Timothy Pearson | 74b13a5 | 2015-10-31 15:00:23 -0500 | [diff] [blame] | 248 | post_code(0x36); |
| 249 | |
| 250 | /* Setup any mainboard PCI settings etc. */ |
| 251 | setup_mb_resource_map(); |
| 252 | post_code(0x37); |
Timothy Pearson | ab95702 | 2015-10-28 02:59:40 -0500 | [diff] [blame] | 253 | |
| 254 | if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { |
| 255 | /* Core0 on each node is configured. Now setup any additional cores. */ |
| 256 | printk(BIOS_DEBUG, "start_other_cores()\n"); |
| 257 | start_other_cores(); |
Timothy Pearson | 74b13a5 | 2015-10-31 15:00:23 -0500 | [diff] [blame] | 258 | post_code(0x38); |
Timothy Pearson | ab95702 | 2015-10-28 02:59:40 -0500 | [diff] [blame] | 259 | wait_all_other_cores_started(bsp_apicid); |
Timothy Pearson | 74b13a5 | 2015-10-31 15:00:23 -0500 | [diff] [blame] | 260 | post_code(0x39); |
Timothy Pearson | ab95702 | 2015-10-28 02:59:40 -0500 | [diff] [blame] | 261 | } |
| 262 | |
| 263 | ht_setup_chains_x(sysinfo); |
| 264 | |
| 265 | #if IS_ENABLED(CONFIG_SET_FIDVID) |
| 266 | /* Check to see if processor is capable of changing FIDVID */ |
| 267 | /* otherwise it will throw a GP# when reading FIDVID_STATUS */ |
| 268 | cpuid1 = cpuid(0x80000007); |
| 269 | if ((cpuid1.edx & 0x6) == 0x6) { |
| 270 | msr_t msr; |
| 271 | |
| 272 | /* Read FIDVID_STATUS */ |
| 273 | msr = rdmsr(0xc0010042); |
| 274 | printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); |
| 275 | |
| 276 | enable_fid_change(); |
| 277 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 278 | init_fidvid_bsp(bsp_apicid); |
| 279 | |
| 280 | /* Show final FID and VID */ |
| 281 | msr = rdmsr(0xc0010042); |
| 282 | printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); |
| 283 | } else { |
| 284 | printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); |
| 285 | } |
| 286 | #endif |
| 287 | |
Timothy Pearson | 74b13a5 | 2015-10-31 15:00:23 -0500 | [diff] [blame] | 288 | init_timer(); /* Need to use TMICT to synchronize FID/VID. */ |
| 289 | |
Timothy Pearson | ab95702 | 2015-10-28 02:59:40 -0500 | [diff] [blame] | 290 | printk(BIOS_DEBUG, "set_ck804_base_unit_id()\n"); |
| 291 | ck804_control(ctrl_conf_fix_pci_numbering, ARRAY_SIZE(ctrl_conf_fix_pci_numbering), CK804_BOARD_BOOT_BASE_UNIT_UID); |
| 292 | |
Timothy Pearson | 74b13a5 | 2015-10-31 15:00:23 -0500 | [diff] [blame] | 293 | post_code(0x3a); |
Timothy Pearson | ab95702 | 2015-10-28 02:59:40 -0500 | [diff] [blame] | 294 | |
| 295 | printk(BIOS_DEBUG, "optimize_link_coherent_ht()\n"); |
| 296 | needs_reset = optimize_link_coherent_ht(); |
| 297 | printk(BIOS_DEBUG, "optimize_link_incoherent_ht()\n"); |
| 298 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
Timothy Pearson | 74b13a5 | 2015-10-31 15:00:23 -0500 | [diff] [blame] | 299 | printk(BIOS_DEBUG, "ck804_early_setup_x()\n"); |
| 300 | needs_reset |= ck804_early_setup_x(); |
Timothy Pearson | ab95702 | 2015-10-28 02:59:40 -0500 | [diff] [blame] | 301 | |
| 302 | /* FIDVID change will issue one LDTSTOP and the HT change will be effective too */ |
| 303 | if (needs_reset) { |
| 304 | printk(BIOS_INFO, "ht reset -\n"); |
| 305 | soft_reset(); |
| 306 | } |
| 307 | |
Timothy Pearson | ab95702 | 2015-10-28 02:59:40 -0500 | [diff] [blame] | 308 | post_code(0x3b); |
| 309 | |
| 310 | allow_all_aps_stop(bsp_apicid); |
| 311 | |
| 312 | /* It's the time to set ctrl in sysinfo now; */ |
| 313 | printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); |
| 314 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 315 | post_code(0x3d); |
| 316 | |
| 317 | printk(BIOS_DEBUG, "enable_smbus()\n"); |
| 318 | enable_smbus(); |
| 319 | |
| 320 | #if 0 |
| 321 | /* FIXME |
| 322 | * After the AMD K10 code has been converted to use |
| 323 | * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block |
| 324 | */ |
| 325 | if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) { |
| 326 | dump_spd_registers(&cpu[0]); |
| 327 | dump_smbus_registers(); |
| 328 | } |
| 329 | #endif |
| 330 | |
| 331 | post_code(0x40); |
| 332 | |
| 333 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 334 | printk(BIOS_DEBUG, "sdram_initialize()\n"); |
| 335 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 336 | |
| 337 | timestamp_add_now(TS_AFTER_INITRAM); |
| 338 | |
| 339 | cbmem_initialize_empty(); |
| 340 | post_code(0x41); |
| 341 | |
| 342 | printk(BIOS_DEBUG, "disable_spd()\n"); |
| 343 | ck804_control(ctrl_conf_disable_spd, ARRAY_SIZE(ctrl_conf_disable_spd), CK804_DEVN_BASE); |
| 344 | |
| 345 | printk(BIOS_DEBUG, "enable_msi_mapping()\n"); |
| 346 | ck804_control(ctrl_conf_enable_msi_mapping, ARRAY_SIZE(ctrl_conf_enable_msi_mapping), CK804_DEVN_BASE); |
| 347 | |
| 348 | /* Initialize GPIO */ |
| 349 | /* Access SuperIO GPI03 logical device */ |
| 350 | uint16_t port = GPIO3_DEV >> 8; |
| 351 | outb(0x87, port); |
| 352 | outb(0x87, port); |
| 353 | pnp_set_logical_device(GPIO3_DEV); |
| 354 | /* Set GP37 (power LED) to output */ |
| 355 | pnp_write_config(GPIO3_DEV, 0xf0, 0x7f); |
| 356 | /* Set GP37 (power LED) on */ |
| 357 | pnp_write_config(GPIO3_DEV, 0xf1, 0x80); |
| 358 | /* Set pin 64 multiplex to GP37 */ |
| 359 | uint8_t cr2c = pnp_read_config(GPIO3_DEV, 0x2c); |
| 360 | pnp_write_config(GPIO3_DEV, 0x2c, (cr2c & 0xf3) | 0x04); |
| 361 | /* Restore default SuperIO access */ |
| 362 | outb(0xaa, port); |
| 363 | |
| 364 | post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. |
| 365 | post_code(0x43); // Should never see this post code. |
| 366 | } |