Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
| 5 | * Copyright (C) 2007 AMD |
| 6 | * (Written by Yinghai Lu <yinghailu@amd.com> for AMD) |
| 7 | * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de> |
| 8 | * (Thanks to LSRA University of Mannheim for their support) |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 19 | */ |
| 20 | |
| 21 | #include <console/console.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pci_ids.h> |
| 24 | #include <string.h> |
| 25 | #include <stdint.h> |
| 26 | #include <stdlib.h> |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 27 | #include <cpu/amd/multicore.h> |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 28 | #include <cpu/amd/amdfam10_sysconf.h> |
| 29 | #include <stdlib.h> |
| 30 | |
| 31 | /* |
| 32 | * Global variables for MB layouts and these will be shared by irqtable, |
| 33 | * mptable and acpi_tables. |
| 34 | */ |
| 35 | /* busnum is default */ |
| 36 | unsigned char bus_ck804[6]; |
| 37 | unsigned apicid_ck804; |
| 38 | |
| 39 | /* Here you only need to set value in pci1234 for HT-IO that could be |
| 40 | installed or not You may need to preset pci1234 for HTIO board, please |
| 41 | refer to src/northbridge/amd/amdfam10/get_pci1234.c for detail */ |
| 42 | static u32 pci1234x[] = { |
| 43 | 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, |
| 44 | 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, |
| 45 | 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, |
| 46 | 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, |
| 47 | 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, |
| 48 | 0x0000ffc, 0x0000ffc, |
| 49 | }; |
| 50 | |
| 51 | |
| 52 | /* HT Chain device num, actually it is unit id base of every ht device |
| 53 | in chain, assume every chain only have 4 ht device at most */ |
| 54 | |
| 55 | static unsigned hcdnx[] = { |
| 56 | 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, |
| 57 | 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, |
| 58 | 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, |
| 59 | 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, |
| 60 | 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, |
| 61 | 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, |
| 62 | 0x20202020, 0x20202020, |
| 63 | }; |
| 64 | |
| 65 | extern void get_pci1234(void); |
| 66 | |
| 67 | static unsigned get_bus_conf_done = 0; |
| 68 | |
| 69 | void get_bus_conf(void) |
| 70 | { |
| 71 | unsigned apicid_base, sbdn; |
| 72 | device_t dev; |
| 73 | int i; |
| 74 | |
| 75 | if (get_bus_conf_done == 1) |
| 76 | return; /* Do it only once. */ |
| 77 | |
| 78 | get_bus_conf_done = 1; |
| 79 | |
| 80 | sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); |
| 81 | for (i = 0; i < sysconf.hc_possible_num; i++) { |
| 82 | sysconf.pci1234[i] = pci1234x[i]; |
| 83 | sysconf.hcdn[i] = hcdnx[i]; |
| 84 | } |
| 85 | |
| 86 | get_pci1234(); |
| 87 | |
| 88 | sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain |
| 89 | sbdn = sysconf.sbdn; |
| 90 | |
| 91 | for (i = 0; i < 6; i++) |
| 92 | bus_ck804[i] = 0; |
| 93 | |
| 94 | /* CK804 */ |
| 95 | dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x09, 0)); |
| 96 | if (dev) { |
| 97 | bus_ck804[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); |
| 98 | bus_ck804[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS); |
| 99 | bus_ck804[2]++; |
| 100 | } else { |
| 101 | printk |
| 102 | (BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", |
| 103 | sbdn + 0x09); |
| 104 | bus_ck804[1] = 2; |
| 105 | bus_ck804[2] = 3; |
| 106 | } |
| 107 | |
| 108 | for (i = 2; i < 6; i++) { |
| 109 | dev = dev_find_slot(bus_ck804[0], |
| 110 | PCI_DEVFN(sbdn + 0x0b + i - 2, 0)); |
| 111 | if (dev) { |
| 112 | bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); |
| 113 | } else { |
| 114 | printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", |
| 115 | bus_ck804[0], sbdn + 0x0b + i - 2); |
| 116 | } |
| 117 | } |
| 118 | |
| 119 | if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { |
| 120 | apicid_base = get_apicid_base(1); |
| 121 | printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==1: apicid_base: %08x\n", apicid_base); |
| 122 | } |
| 123 | else { |
| 124 | apicid_base = CONFIG_MAX_PHYSICAL_CPUS; |
| 125 | printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==0: apicid_base: %08x\n", apicid_base); |
| 126 | } |
| 127 | apicid_ck804 = apicid_base + 0; |
| 128 | } |