Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
| 4 | # Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | # |
| 6 | # This program is free software; you can redistribute it and/or modify |
| 7 | # it under the terms of the GNU General Public License as published by |
| 8 | # the Free Software Foundation; version 2 of the License. |
| 9 | # |
| 10 | # This program is distributed in the hope that it will be useful, |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | # GNU General Public License for more details. |
| 14 | # |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 15 | chip northbridge/amd/agesa/family14/root_complex |
Edward O'Callaghan | dfa8a32 | 2014-04-29 20:03:31 +1000 | [diff] [blame] | 16 | device cpu_cluster 0 on |
| 17 | chip cpu/amd/agesa/family14 |
Paul Menzel | e72645a | 2014-04-29 23:31:55 +0200 | [diff] [blame] | 18 | device lapic 0 on end |
Edward O'Callaghan | dfa8a32 | 2014-04-29 20:03:31 +1000 | [diff] [blame] | 19 | end |
| 20 | end |
| 21 | device domain 0 on |
| 22 | subsystemid 0x1022 0x1510 inherit |
| 23 | chip northbridge/amd/agesa/family14 # CPU side of HT root complex |
| 24 | # device pci 18.0 on # northbridge |
| 25 | chip northbridge/amd/agesa/family14 # PCI side of HT root complex |
| 26 | device pci 0.0 on end # Root Complex |
| 27 | device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 28 | |
Edward O'Callaghan | dfa8a32 | 2014-04-29 20:03:31 +1000 | [diff] [blame] | 29 | device pci 1.1 on end # Internal HDMI Audio |
| 30 | device pci 4.0 on end # PCIE P2P bridge 0x9604 |
| 31 | device pci 5.0 off end # PCIE P2P bridge 0x9605 |
| 32 | device pci 6.0 off end # PCIE P2P bridge 0x9606 |
| 33 | device pci 7.0 off end # PCIE P2P bridge 0x9607 |
| 34 | device pci 8.0 off end # NB/SB Link P2P bridge |
| 35 | end # agesa northbridge |
| 36 | |
| 37 | chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus |
| 38 | device pci 11.0 on end # SATA |
| 39 | device pci 12.0 on end # USB |
| 40 | device pci 12.2 on end # USB |
| 41 | device pci 13.0 on end # USB |
| 42 | device pci 13.2 on end # USB |
| 43 | device pci 14.0 on # SM |
| 44 | chip drivers/generic/generic #dimm 0-0-0 |
| 45 | device i2c 50 on end |
| 46 | end |
| 47 | chip drivers/generic/generic #dimm 0-0-1 |
| 48 | device i2c 51 on end |
| 49 | end |
| 50 | end # SM |
| 51 | device pci 14.1 on end # IDE 0x439c |
| 52 | device pci 14.2 on end # HDA 0x4383 |
Felix Held | c186966 | 2014-07-19 00:21:43 +0200 | [diff] [blame] | 53 | device pci 14.3 on # LPC |
| 54 | chip superio/nuvoton/nct5572d |
| 55 | device pnp 2e.0 off end # FDC; not externally available on the NCT5572D, but on the die |
| 56 | device pnp 2e.1 off end # LPT1; same as FDC |
Scott Duplichan | 63896e7 | 2011-02-26 17:49:49 +0000 | [diff] [blame] | 57 | device pnp 2e.2 on # Com1 |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 58 | io 0x60 = 0x3f8 |
| 59 | irq 0x70 = 4 |
| 60 | end |
Felix Held | c186966 | 2014-07-19 00:21:43 +0200 | [diff] [blame] | 61 | device pnp 2e.3 off # IR |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 62 | io 0x60 = 0x2f8 |
| 63 | irq 0x70 = 3 |
| 64 | end |
Scott Duplichan | 63896e7 | 2011-02-26 17:49:49 +0000 | [diff] [blame] | 65 | device pnp 2e.5 on # Keyboard |
| 66 | io 0x60 = 0x60 |
| 67 | io 0x62 = 0x64 |
| 68 | irq 0x70 = 1 |
| 69 | irq 0x72 = 12 |
| 70 | end |
| 71 | device pnp 2e.6 off # CIR |
| 72 | io 0x60 = 0x100 |
Felix Held | c186966 | 2014-07-19 00:21:43 +0200 | [diff] [blame] | 73 | irq 0x70 = 0 |
Scott Duplichan | 63896e7 | 2011-02-26 17:49:49 +0000 | [diff] [blame] | 74 | end |
Kyösti Mälkki | d28474b | 2015-10-28 11:08:24 +0200 | [diff] [blame] | 75 | device pnp 2e.107 off end # GPIO6 |
| 76 | device pnp 2e.207 off end # GPIO7 |
| 77 | device pnp 2e.307 on # GPIO8 |
| 78 | irq 0x23 = 0x28 |
| 79 | irq 0xe4 = 0xbf |
| 80 | irq 0xed = 0x27 |
| 81 | end |
| 82 | device pnp 2e.407 off end # GPIO9 |
Felix Held | c186966 | 2014-07-19 00:21:43 +0200 | [diff] [blame] | 83 | device pnp 2e.8 off end # WDT |
Kyösti Mälkki | d28474b | 2015-10-28 11:08:24 +0200 | [diff] [blame] | 84 | device pnp 2e.009 on # GPIO2 |
| 85 | irq 0x2a = 0x42 |
| 86 | irq 0xe0 = 0xe3 |
| 87 | end |
| 88 | device pnp 2e.109 off end # GPIO3 |
| 89 | device pnp 2e.209 off end # GPIO4 |
| 90 | device pnp 2e.309 off end # GPIO5 |
| 91 | device pnp 2e.a on # ACPI |
| 92 | irq 0xe7 = 0x10 |
| 93 | end |
Scott Duplichan | 63896e7 | 2011-02-26 17:49:49 +0000 | [diff] [blame] | 94 | device pnp 2e.b on # HW Monitor |
| 95 | io 0x60 = 0x290 |
Felix Held | c186966 | 2014-07-19 00:21:43 +0200 | [diff] [blame] | 96 | io 0x62 = 0x0000 # SB-TSI currently not implemented |
Scott Duplichan | 63896e7 | 2011-02-26 17:49:49 +0000 | [diff] [blame] | 97 | irq 0x70 = 5 |
| 98 | end |
Felix Held | c186966 | 2014-07-19 00:21:43 +0200 | [diff] [blame] | 99 | device pnp 2e.c off end # PECI |
Kyösti Mälkki | d28474b | 2015-10-28 11:08:24 +0200 | [diff] [blame] | 100 | device pnp 2e.d on # SUSLED |
| 101 | irq 0xec = 0x90 |
| 102 | end |
Felix Held | c186966 | 2014-07-19 00:21:43 +0200 | [diff] [blame] | 103 | device pnp 2e.e off # CIRWKUP |
| 104 | io 0x60 = 0x0000 |
| 105 | irq 0x70 = 0 |
| 106 | end |
| 107 | device pnp 2e.f off end # GPIO_PP_OD |
Scott Duplichan | 63896e7 | 2011-02-26 17:49:49 +0000 | [diff] [blame] | 108 | end |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 109 | end #LPC |
Kerry She | 3e706b6 | 2011-06-24 22:52:15 +0800 | [diff] [blame] | 110 | device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} |
Edward O'Callaghan | dfa8a32 | 2014-04-29 20:03:31 +1000 | [diff] [blame] | 111 | device pci 14.5 on end # USB 2 |
Scott Duplichan | 8fed77a | 2011-06-18 10:46:45 -0500 | [diff] [blame] | 112 | device pci 15.0 on end # PCIe PortA |
Marshall Buschman | b531e4e | 2011-06-18 12:04:41 -0500 | [diff] [blame] | 113 | device pci 15.1 on end # PCIe PortB: NIC |
| 114 | device pci 15.2 on end # PCIe PortC: USB3 |
Peter Stuge | 2334c8d | 2011-06-04 15:47:30 +0000 | [diff] [blame] | 115 | device pci 15.3 off end # PCIe PortD |
Kerry Sheh | 75df106 | 2011-10-10 19:19:46 +0800 | [diff] [blame] | 116 | device pci 16.0 off end # OHCI USB3 |
| 117 | device pci 16.2 off end # EHCI USB3 |
Scott Duplichan | 8fed77a | 2011-06-18 10:46:45 -0500 | [diff] [blame] | 118 | |
| 119 | # gpp_configuration options |
| 120 | #0000: PortA lanes[3:0] |
| 121 | #0001: N/A |
| 122 | #0010: PortA lanes[1:0], PortB lanes[3:2] |
| 123 | #0011: PortA lanes[1:0], PortB lane2, PortC lane3 |
| 124 | #0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3. |
| 125 | register "gpp_configuration" = "4" |
| 126 | |
Edward O'Callaghan | dfa8a32 | 2014-04-29 20:03:31 +1000 | [diff] [blame] | 127 | register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 128 | end #southbridge/amd/cimx/sb800 |
Edward O'Callaghan | dfa8a32 | 2014-04-29 20:03:31 +1000 | [diff] [blame] | 129 | # end # device pci 18.0 |
| 130 | # |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 131 | # These seem unnecessary |
Edward O'Callaghan | dfa8a32 | 2014-04-29 20:03:31 +1000 | [diff] [blame] | 132 | device pci 18.0 on end |
| 133 | device pci 18.1 on end |
| 134 | device pci 18.2 on end |
| 135 | device pci 18.3 on end |
| 136 | device pci 18.4 on end |
| 137 | device pci 18.5 on end |
| 138 | device pci 18.6 on end |
| 139 | device pci 18.7 on end |
Jens Rottmann | db6c5bf | 2013-03-21 22:21:28 +0100 | [diff] [blame] | 140 | |
| 141 | register "spdAddrLookup" = " |
| 142 | { |
| 143 | { {0xA0, 0xA4}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses |
| 144 | { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses |
| 145 | }" |
| 146 | |
Edward O'Callaghan | dfa8a32 | 2014-04-29 20:03:31 +1000 | [diff] [blame] | 147 | end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex |
| 148 | end #domain |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 149 | end #northbridge/amd/agesa/family14/root_complex |