Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include "AGESA.h" |
| 17 | #include "amdlib.h" |
| 18 | #include "Ids.h" |
| 19 | #include "heapManager.h" |
| 20 | #include "PlatformGnbPcieComplex.h" |
| 21 | #include "Filecode.h" |
| 22 | |
Edward O'Callaghan | 8864e1c | 2014-04-30 23:13:08 +1000 | [diff] [blame] | 23 | #include <string.h> |
Kyösti Mälkki | 34ad72c | 2014-10-21 13:43:46 +0300 | [diff] [blame] | 24 | #include <northbridge/amd/agesa/agesawrapper.h> |
Edward O'Callaghan | 8864e1c | 2014-04-30 23:13:08 +1000 | [diff] [blame] | 25 | |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 26 | #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE |
| 27 | |
| 28 | /*---------------------------------------------------------------------------------------*/ |
| 29 | /** |
| 30 | * OemCustomizeInitEarly |
| 31 | * |
| 32 | * Description: |
Paul Menzel | 63950f8 | 2013-02-01 23:51:40 +0100 | [diff] [blame] | 33 | * This stub function will call the host environment through the binary block |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 34 | * interface (call-out port) to provide a user hook opportunity |
| 35 | * |
| 36 | * Parameters: |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 37 | * @param[in] *InitEarly |
| 38 | * |
| 39 | * @retval VOID |
| 40 | * |
| 41 | **/ |
| 42 | /*---------------------------------------------------------------------------------------*/ |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 43 | |
| 44 | static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 45 | { |
| 46 | AGESA_STATUS Status; |
| 47 | VOID *BrazosPcieComplexListPtr; |
| 48 | VOID *BrazosPciePortPtr; |
| 49 | VOID *BrazosPcieDdiPtr; |
| 50 | |
| 51 | ALLOCATE_HEAP_PARAMS AllocHeapParams; |
| 52 | |
| 53 | PCIe_PORT_DESCRIPTOR PortList [] = { |
| 54 | // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) |
| 55 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 56 | 0, |
Kyösti Mälkki | 2e3bdcf7 | 2015-01-15 17:42:53 +0200 | [diff] [blame] | 57 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), |
Paul Menzel | e988b51 | 2013-02-23 00:15:49 +0100 | [diff] [blame] | 58 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 59 | }, |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 60 | // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) |
| 61 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 62 | DESCRIPTOR_TERMINATE_LIST, |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 63 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), |
| 64 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 65 | } |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 66 | }; |
| 67 | |
| 68 | PCIe_DDI_DESCRIPTOR DdiList [] = { |
| 69 | // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) |
| 70 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 71 | 0, |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 72 | PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), |
| 73 | //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) |
| 74 | {ConnectorTypeDP, Aux1, Hdp1} |
| 75 | }, |
| 76 | // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) |
| 77 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 78 | DESCRIPTOR_TERMINATE_LIST, |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 79 | PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), |
| 80 | //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) |
| 81 | {ConnectorTypeDP, Aux2, Hdp2} |
| 82 | } |
| 83 | }; |
| 84 | |
| 85 | PCIe_COMPLEX_DESCRIPTOR Brazos = { |
| 86 | DESCRIPTOR_TERMINATE_LIST, |
| 87 | 0, |
| 88 | &PortList[0], |
| 89 | &DdiList[0] |
| 90 | }; |
| 91 | |
| 92 | // GNB PCIe topology Porting |
| 93 | |
| 94 | // |
| 95 | // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR |
| 96 | // |
Paul Menzel | d189229 | 2013-05-14 10:06:47 +0200 | [diff] [blame] | 97 | AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 98 | |
| 99 | AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; |
| 100 | AllocHeapParams.Persist = HEAP_LOCAL_CACHE; |
| 101 | Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); |
Kyösti Mälkki | 1ef67e1 | 2014-12-16 16:45:52 +0200 | [diff] [blame] | 102 | ASSERT(Status == AGESA_SUCCESS); |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 103 | |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 104 | BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; |
| 105 | |
Paul Menzel | d189229 | 2013-05-14 10:06:47 +0200 | [diff] [blame] | 106 | AllocHeapParams.BufferPtr += sizeof(Brazos); |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 107 | BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; |
| 108 | |
Paul Menzel | d189229 | 2013-05-14 10:06:47 +0200 | [diff] [blame] | 109 | AllocHeapParams.BufferPtr += sizeof(PortList); |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 110 | BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 111 | |
Edward O'Callaghan | 8864e1c | 2014-04-30 23:13:08 +1000 | [diff] [blame] | 112 | memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); |
| 113 | memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); |
| 114 | memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 115 | |
| 116 | |
| 117 | ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; |
| 118 | ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; |
| 119 | |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 120 | InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; |
| 121 | InitEarly->GnbConfig.PsppPolicy = 0; |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 122 | return AGESA_SUCCESS; |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 123 | } |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 124 | |
| 125 | const struct OEM_HOOK OemCustomize = { |
| 126 | .InitEarly = OemInitEarly, |
| 127 | }; |