efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | /** |
| 17 | * @file |
| 18 | * |
| 19 | * AMD User options selection for a Sabine/Lynx platform solution system |
| 20 | * |
| 21 | * This file is placed in the user's platform directory and contains the |
| 22 | * build option selections desired for that platform. |
| 23 | * |
| 24 | * For Information about this file, see @ref platforminstall. |
| 25 | * |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 26 | */ |
Edward O'Callaghan | d5339ae | 2014-07-07 19:58:53 +1000 | [diff] [blame] | 27 | |
| 28 | #include <stdlib.h> |
Elyes HAOUAS | aedcc10 | 2014-07-21 08:07:19 +0200 | [diff] [blame] | 29 | #include "AGESA.h" |
| 30 | #include "CommonReturns.h" |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 31 | #include "Filecode.h" |
| 32 | #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE |
| 33 | |
| 34 | |
| 35 | /* Select the cpu family. */ |
| 36 | #define INSTALL_FAMILY_10_SUPPORT FALSE |
| 37 | #define INSTALL_FAMILY_12_SUPPORT TRUE |
| 38 | #define INSTALL_FAMILY_14_SUPPORT FALSE |
| 39 | #define INSTALL_FAMILY_15_SUPPORT FALSE |
| 40 | |
| 41 | /* Select the cpu socket type. */ |
| 42 | #define INSTALL_G34_SOCKET_SUPPORT FALSE |
| 43 | #define INSTALL_C32_SOCKET_SUPPORT FALSE |
| 44 | #define INSTALL_S1G3_SOCKET_SUPPORT FALSE |
| 45 | #define INSTALL_S1G4_SOCKET_SUPPORT FALSE |
| 46 | #define INSTALL_ASB2_SOCKET_SUPPORT FALSE |
| 47 | #define INSTALL_FS1_SOCKET_SUPPORT TRUE |
| 48 | #define INSTALL_FM1_SOCKET_SUPPORT FALSE |
| 49 | #define INSTALL_FP1_SOCKET_SUPPORT TRUE |
| 50 | #define INSTALL_FT1_SOCKET_SUPPORT FALSE |
| 51 | #define INSTALL_AM3_SOCKET_SUPPORT FALSE |
| 52 | |
| 53 | /* |
| 54 | * Agesa optional capabilities selection. |
| 55 | * Uncomment and mark FALSE those features you wish to include in the build. |
| 56 | * Comment out or mark TRUE those features you want to REMOVE from the build. |
| 57 | */ |
| 58 | |
| 59 | #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE |
| 60 | #define BLDOPT_REMOVE_RDIMMS_SUPPORT FALSE |
| 61 | #define BLDOPT_REMOVE_ECC_SUPPORT FALSE |
| 62 | #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE |
| 63 | #define BLDOPT_REMOVE_DCT_INTERLEAVE FALSE |
| 64 | #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE |
| 65 | #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE |
| 66 | #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE |
| 67 | #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE |
| 68 | #define BLDOPT_REMOVE_DDR2_SUPPORT TRUE |
| 69 | #define BLDOPT_REMOVE_DDR3_SUPPORT FALSE |
| 70 | #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE |
| 71 | #define BLDOPT_REMOVE_ACPI_PSTATES FALSE |
| 72 | #define BLDOPT_REMOVE_SRAT TRUE |
| 73 | #define BLDOPT_REMOVE_SLIT TRUE |
| 74 | #define BLDOPT_REMOVE_WHEA TRUE |
| 75 | #define BLDOPT_REMOVE_DMI FALSE |
| 76 | #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE |
| 77 | #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE |
| 78 | #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE |
| 79 | #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE |
| 80 | #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE |
| 81 | #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE |
| 82 | |
| 83 | //For revision C single-link processors |
| 84 | #define BLDCFG_SUPPORT_ACPI_PSTATES_PSD_INDPX TRUE |
| 85 | |
| 86 | /* |
| 87 | * Agesa entry points used in this implementation. |
| 88 | */ |
| 89 | #define AGESA_ENTRY_INIT_RESET TRUE |
| 90 | #define AGESA_ENTRY_INIT_RECOVERY FALSE |
| 91 | #define AGESA_ENTRY_INIT_EARLY TRUE |
| 92 | #define AGESA_ENTRY_INIT_POST TRUE |
| 93 | #define AGESA_ENTRY_INIT_ENV TRUE |
| 94 | #define AGESA_ENTRY_INIT_MID TRUE |
| 95 | #define AGESA_ENTRY_INIT_LATE TRUE |
| 96 | #define AGESA_ENTRY_INIT_S3SAVE TRUE |
| 97 | #define AGESA_ENTRY_INIT_RESUME TRUE |
| 98 | #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE |
| 99 | #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE |
| 100 | |
| 101 | /***************************************************************************** |
| 102 | * Define the RELEASE VERSION string |
| 103 | * |
| 104 | * The Release Version string should identify the next planned release. |
| 105 | * When a branch is made in preparation for a release, the release manager |
| 106 | * should change/confirm that the branch version of this file contains the |
| 107 | * string matching the desired version for the release. The trunk version of |
| 108 | * the file should always contain a trailing 'X'. This will make sure that a |
| 109 | * development build from trunk will not be confused for a released version. |
| 110 | * The release manager will need to remove the trailing 'X' and update the |
| 111 | * version string as appropriate for the release. The trunk copy of this file |
| 112 | * should also be updated/incremented for the next expected version, + trailing 'X' |
| 113 | ****************************************************************************/ |
| 114 | // This is the delivery package title, "LlanoPI " |
| 115 | // This string MUST be exactly 8 characters long |
| 116 | #define AGESA_PACKAGE_STRING {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '} |
| 117 | |
| 118 | // This is the release version number of the AGESA component |
| 119 | // This string MUST be exactly 12 characters long |
| 120 | #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '} |
| 121 | |
| 122 | // The following definitions specify the default values for various parameters in which there are |
| 123 | // no clearly defined defaults to be used in the common file. The values below are based on product |
| 124 | // and BKDG content, please consult the AGESA Memory team for consultation. |
| 125 | #define DFLT_SCRUB_DRAM_RATE (0) |
| 126 | #define DFLT_SCRUB_L2_RATE (0) |
| 127 | #define DFLT_SCRUB_L3_RATE (0) |
| 128 | #define DFLT_SCRUB_IC_RATE (0) |
| 129 | #define DFLT_SCRUB_DC_RATE (0) |
| 130 | #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED |
| 131 | #define DFLT_VRM_SLEW_RATE (5000) |
| 132 | |
| 133 | /* Build configuration values here. |
| 134 | */ |
| 135 | #define BLDCFG_VRM_CURRENT_LIMIT 65000 //240000 //120000 |
| 136 | #define BLDCFG_VRM_LOW_POWER_THRESHOLD 15000 // 0 |
| 137 | #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0 |
| 138 | #define BLDCFG_PLAT_NUM_IO_APICS 3 |
| 139 | #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST |
| 140 | #define BLDCFG_MEM_INIT_PSTATE 0 |
| 141 | |
| 142 | #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE |
| 143 | |
| 144 | #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY //DDR1066_FREQUENCY |
| 145 | #define BLDCFG_MEMORY_MODE_UNGANGED TRUE |
| 146 | #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE |
| 147 | #define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED |
| 148 | #define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE |
| 149 | #define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE |
| 150 | #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE |
| 151 | #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE |
| 152 | #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE |
| 153 | #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE |
| 154 | #define BLDCFG_MEMORY_POWER_DOWN TRUE |
| 155 | #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT |
| 156 | #define BLDCFG_ONLINE_SPARE FALSE |
| 157 | #define BLDCFG_MEMORY_PARITY_ENABLE FALSE |
| 158 | #define BLDCFG_BANK_SWIZZLE TRUE |
| 159 | #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO |
| 160 | #define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY |
| 161 | #define BLDCFG_DQS_TRAINING_CONTROL TRUE |
| 162 | #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE |
| 163 | #define BLDCFG_USE_BURST_MODE FALSE |
| 164 | #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE |
| 165 | #define BLDCFG_ENABLE_ECC_FEATURE TRUE |
| 166 | #define BLDCFG_ECC_REDIRECTION FALSE |
| 167 | #define BLDCFG_SCRUB_DRAM_RATE 0 |
| 168 | #define BLDCFG_SCRUB_L2_RATE 0 |
| 169 | #define BLDCFG_SCRUB_L3_RATE 0 |
| 170 | #define BLDCFG_SCRUB_IC_RATE 0 |
| 171 | #define BLDCFG_SCRUB_DC_RATE 0 |
| 172 | #define BLDCFG_ECC_SYNC_FLOOD FALSE |
| 173 | #define BLDCFG_ECC_SYMBOL_SIZE 4 |
| 174 | #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 |
| 175 | #define BLDCFG_1GB_ALIGN FALSE |
| 176 | #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE |
| 177 | //#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' |
| 178 | //#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' |
| 179 | |
| 180 | //enable HW C1E |
| 181 | #define BLDCFG_PLATFORM_C1E_MODE 0 //C1eModeHardware |
| 182 | //#define BLDCFG_PLATFORM_C1E_OPDATA 0x415 |
| 183 | #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 //0 //CStateModeC6 |
| 184 | //#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6 |
| 185 | #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6 |
| 186 | |
| 187 | |
| 188 | //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario |
| 189 | #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L. Default is Zero. |
| 190 | //#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime per BKDG. Defaults to 5000, same as core VRM. Cannot be zero. |
| 191 | //#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Llano/Ontario |
| 192 | //#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Llano/Ontario |
| 193 | //#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario |
| 194 | |
| 195 | #define BLDCFG_UMA_ABOVE4G_SUPPORT TRUE |
| 196 | #define BLDCFG_STEREO_3D_PINOUT TRUE |
| 197 | |
| 198 | /* Process the options... |
| 199 | * This file include MUST occur AFTER the user option selection settings |
| 200 | */ |
| 201 | CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] = |
| 202 | { |
| 203 | { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, |
| 204 | { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, |
| 205 | { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, |
| 206 | { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull }, |
| 207 | { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull }, |
| 208 | { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull }, |
| 209 | { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull }, |
| 210 | { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull }, |
| 211 | { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull }, |
| 212 | { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull }, |
| 213 | { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull }, |
| 214 | { CPU_LIST_TERMINAL } |
| 215 | }; |
| 216 | |
| 217 | #define BLDCFG_AP_MTRR_SETTINGS_LIST &LlanoApMtrrSettingsList |
| 218 | //#define OPTION_NB_LCLK_DPM_INIT FALSE |
| 219 | //#define OPTION_POWER_GATE FALSE |
| 220 | //#define OPTION_PCIE_POWER_GATE FALSE |
| 221 | //#define OPTION_ALIB FALSE |
| 222 | //#define OPTION_PCIe_MID_INIT FALSE |
| 223 | //#define OPTION_NB_MID_INIT FALSE |
| 224 | |
| 225 | #include "cpuRegisters.h" |
| 226 | #include "cpuFamRegisters.h" |
| 227 | #include "cpuFamilyTranslation.h" |
| 228 | #include "AdvancedApi.h" |
| 229 | #include "heapManager.h" |
| 230 | #include "CreateStruct.h" |
| 231 | #include "cpuFeatures.h" |
| 232 | #include "Table.h" |
| 233 | #include "CommonReturns.h" |
| 234 | #include "cpuEarlyInit.h" |
| 235 | #include "cpuLateInit.h" |
| 236 | #include "GnbInterface.h" |
| 237 | #include "PlatformInstall.h" |
| 238 | |
| 239 | /*---------------------------------------------------------------------------------------- |
| 240 | * CUSTOMER OVERIDES MEMORY TABLE |
| 241 | *---------------------------------------------------------------------------------------- |
| 242 | */ |
| 243 | |
| 244 | /* |
| 245 | * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA |
| 246 | * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable |
| 247 | * is populated, AGESA will base its settings on the data from the table. Otherwise, it will |
| 248 | * use its default conservative settings. |
| 249 | */ |
| 250 | CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { |
| 251 | // |
| 252 | // The following macros are supported (use comma to separate macros): |
| 253 | // |
| 254 | // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) |
| 255 | // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. |
| 256 | // AGESA will base on this value to disable unused MemClk to save power. |
| 257 | // Example: |
| 258 | // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: |
| 259 | // Bit AM3/S1g3 pin name |
| 260 | // 0 M[B,A]_CLK_H/L[0] |
| 261 | // 1 M[B,A]_CLK_H/L[1] |
| 262 | // 2 M[B,A]_CLK_H/L[2] |
| 263 | // 3 M[B,A]_CLK_H/L[3] |
| 264 | // 4 M[B,A]_CLK_H/L[4] |
| 265 | // 5 M[B,A]_CLK_H/L[5] |
| 266 | // 6 M[B,A]_CLK_H/L[6] |
| 267 | // 7 M[B,A]_CLK_H/L[7] |
| 268 | // And platform has the following routing: |
| 269 | // CS0 M[B,A]_CLK_H/L[4] |
| 270 | // CS1 M[B,A]_CLK_H/L[2] |
| 271 | // CS2 M[B,A]_CLK_H/L[3] |
| 272 | // CS3 M[B,A]_CLK_H/L[5] |
| 273 | // Then platform can specify the following macro: |
| 274 | // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) |
| 275 | // |
| 276 | // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) |
| 277 | // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. |
| 278 | // AGESA will base on this value to tristate unused CKE to save power. |
| 279 | // |
| 280 | // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) |
| 281 | // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. |
| 282 | // AGESA will base on this value to tristate unused ODT pins to save power. |
| 283 | // |
| 284 | // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) |
| 285 | // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. |
| 286 | // AGESA will base on this value to tristate unused Chip select to save power. |
| 287 | // |
| 288 | // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) |
| 289 | // Specifies the number of DIMM slots per channel. |
| 290 | // |
| 291 | // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) |
| 292 | // Specifies the number of Chip selects per channel. |
| 293 | // |
| 294 | // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) |
| 295 | // Specifies the number of channels per socket. |
| 296 | // |
| 297 | // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) |
| 298 | // Specifies DDR bus speed of channel ChannelID on socket SocketID. |
| 299 | // |
| 300 | // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) |
| 301 | // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) |
| 302 | // |
| 303 | // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, |
| 304 | // Byte6Seed, Byte7Seed, ByteEccSeed) |
| 305 | // Specifies the write leveling seed for a channel of a socket. |
| 306 | // |
| 307 | NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), |
| 308 | NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), |
| 309 | PSO_END |
| 310 | }; |
| 311 | |
| 312 | /* |
| 313 | * These tables are optional and may be used to adjust memory timing settings |
| 314 | */ |
| 315 | #include "mm.h" |
| 316 | #include "mn.h" |