efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
Kyösti Mälkki | 526c2fb | 2014-07-10 22:16:58 +0300 | [diff] [blame] | 16 | #include "AGESA.h" |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 17 | #include "amdlib.h" |
Kyösti Mälkki | 26f297e | 2014-05-26 11:27:54 +0300 | [diff] [blame] | 18 | #include <northbridge/amd/agesa/BiosCallOuts.h> |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 19 | #include "Ids.h" |
| 20 | #include "OptionsIds.h" |
| 21 | #include "heapManager.h" |
| 22 | #include "Hudson-2.h" |
Kyösti Mälkki | 6025efa | 2014-05-05 13:20:56 +0300 | [diff] [blame] | 23 | #include <stdlib.h> |
Kyösti Mälkki | 50c9637 | 2014-10-18 07:51:03 +0300 | [diff] [blame] | 24 | #include <southbridge/amd/cimx/sb700/gpio_oem.h> |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 25 | |
Stefan Reinauer | dd132a5 | 2015-07-30 11:16:37 -0700 | [diff] [blame] | 26 | static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); |
| 27 | static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); |
Kyösti Mälkki | c009601 | 2014-05-05 18:56:33 +0300 | [diff] [blame] | 28 | |
Kyösti Mälkki | 6025efa | 2014-05-05 13:20:56 +0300 | [diff] [blame] | 29 | const BIOS_CALLOUT_STRUCT BiosCallouts[] = |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 30 | { |
Kyösti Mälkki | 5e19fa4 | 2014-05-04 23:13:54 +0300 | [diff] [blame] | 31 | {AGESA_DO_RESET, agesa_Reset }, |
Kyösti Mälkki | a1ebbc4 | 2014-10-17 22:33:22 +0300 | [diff] [blame] | 32 | {AGESA_READ_SPD, agesa_ReadSpd }, |
Kyösti Mälkki | c459f96 | 2014-05-04 17:07:45 +0300 | [diff] [blame] | 33 | {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, |
Kyösti Mälkki | 6b4b151 | 2014-05-05 12:05:53 +0300 | [diff] [blame] | 34 | {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, |
Kyösti Mälkki | c009601 | 2014-05-05 18:56:33 +0300 | [diff] [blame] | 35 | {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, |
Kyösti Mälkki | c459f96 | 2014-05-04 17:07:45 +0300 | [diff] [blame] | 36 | {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, |
Kyösti Mälkki | c009601 | 2014-05-05 18:56:33 +0300 | [diff] [blame] | 37 | {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, |
Kyösti Mälkki | c459f96 | 2014-05-04 17:07:45 +0300 | [diff] [blame] | 38 | {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, |
| 39 | {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, |
| 40 | {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 41 | }; |
Kyösti Mälkki | 6025efa | 2014-05-05 13:20:56 +0300 | [diff] [blame] | 42 | const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 43 | |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 44 | /* Call the host environment interface to provide a user hook opportunity. */ |
Stefan Reinauer | dd132a5 | 2015-07-30 11:16:37 -0700 | [diff] [blame] | 45 | static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 46 | { |
| 47 | AGESA_STATUS Status; |
| 48 | UINTN FcnData; |
| 49 | MEM_DATA_STRUCT *MemData; |
| 50 | UINT32 AcpiMmioAddr; |
| 51 | UINT32 GpioMmioAddr; |
| 52 | UINT8 Data8; |
| 53 | UINT16 Data16; |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 54 | |
| 55 | FcnData = Data; |
| 56 | MemData = ConfigPtr; |
| 57 | |
| 58 | Status = AGESA_SUCCESS; |
| 59 | /* Get SB MMIO Base (AcpiMmioAddr) */ |
| 60 | WriteIo8 (0xCD6, 0x27); |
| 61 | Data8 = ReadIo8(0xCD7); |
| 62 | Data16 = Data8<<8; |
| 63 | WriteIo8 (0xCD6, 0x26); |
| 64 | Data8 = ReadIo8(0xCD7); |
| 65 | Data16 |= Data8; |
| 66 | AcpiMmioAddr = (UINT32)Data16 << 16; |
| 67 | GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; |
efdesign98 | 2c66060 | 2011-08-19 14:25:48 -0600 | [diff] [blame] | 68 | |
| 69 | switch(MemData->ParameterListPtr->DDR3Voltage){ |
| 70 | case VOLT1_35: |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 71 | Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); |
| 72 | Data8 &= ~(UINT8)BIT6; |
| 73 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); |
| 74 | Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); |
efdesign98 | 2c66060 | 2011-08-19 14:25:48 -0600 | [diff] [blame] | 75 | Data8 |= (UINT8)BIT6; |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 76 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); |
efdesign98 | 2c66060 | 2011-08-19 14:25:48 -0600 | [diff] [blame] | 77 | break; |
| 78 | case VOLT1_25: |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 79 | Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); |
| 80 | Data8 &= ~(UINT8)BIT6; |
| 81 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); |
| 82 | Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); |
| 83 | Data8 &= ~(UINT8)BIT6; |
| 84 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); |
efdesign98 | 2c66060 | 2011-08-19 14:25:48 -0600 | [diff] [blame] | 85 | break; |
| 86 | case VOLT1_5: |
| 87 | default: |
| 88 | Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); |
| 89 | Data8 |= (UINT8)BIT6; |
| 90 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); |
| 91 | } |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 92 | return Status; |
| 93 | } |
| 94 | |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 95 | /* PCIE slot reset control */ |
Stefan Reinauer | dd132a5 | 2015-07-30 11:16:37 -0700 | [diff] [blame] | 96 | static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 97 | { |
| 98 | AGESA_STATUS Status; |
| 99 | UINTN FcnData; |
| 100 | PCIe_SLOT_RESET_INFO *ResetInfo; |
| 101 | |
| 102 | UINT32 GpioMmioAddr; |
| 103 | UINT32 AcpiMmioAddr; |
| 104 | UINT8 Data8; |
| 105 | UINT16 Data16; |
| 106 | |
| 107 | FcnData = Data; |
| 108 | ResetInfo = ConfigPtr; |
| 109 | // Get SB MMIO Base (AcpiMmioAddr) |
| 110 | WriteIo8(0xCD6, 0x27); |
| 111 | Data8 = ReadIo8(0xCD7); |
| 112 | Data16=Data8<<8; |
| 113 | WriteIo8(0xCD6, 0x26); |
| 114 | Data8 = ReadIo8(0xCD7); |
| 115 | Data16|=Data8; |
| 116 | AcpiMmioAddr = (UINT32)Data16 << 16; |
| 117 | Status = AGESA_UNSUPPORTED; |
| 118 | GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; |
| 119 | |
| 120 | if (ResetInfo->ResetControl == DeassertSlotReset) { |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 121 | if (ResetInfo->ResetId & (BIT2+BIT3)) { //de-assert |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 122 | // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH |
| 123 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45); |
| 124 | if (Data8 & BIT7) { |
| 125 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); |
| 126 | while (!(Data8 & BIT7)) { |
| 127 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 128 | } |
efdesign98 | 770b877 | 2011-06-20 21:48:37 -0700 | [diff] [blame] | 129 | // GPIO44: PE_GPIO0 MXM Reset |
| 130 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44); |
| 131 | Data8 |= BIT6 ; |
| 132 | Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8); |
| 133 | Status = AGESA_SUCCESS; |
| 134 | } |
| 135 | } else { |
| 136 | Status = AGESA_UNSUPPORTED; |
| 137 | } |
| 138 | // Travis |
| 139 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24); |
| 140 | Data8 |= BIT6; |
| 141 | Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8); |
| 142 | //DE-Assert ALL PCIE RESET |
| 143 | // APU GPP0 (Dev 4) |
| 144 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); |
| 145 | Data8 |= BIT6 ; |
| 146 | Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); |
| 147 | // APU GPP1 (Dev 5) |
| 148 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01); |
| 149 | Data8 |= BIT6; |
| 150 | Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8); |
| 151 | // APU GPP2 (Dev 6) |
| 152 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00); |
| 153 | Data8 |= BIT6; |
| 154 | Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8); |
| 155 | // APU GPP3 (Dev 7) |
| 156 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27); |
| 157 | Data8 |= BIT6; |
| 158 | Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8); |
| 159 | } else { |
| 160 | if (ResetInfo->ResetId & (BIT2+BIT3)) { //Pcie Slot Reset is supported |
| 161 | // GPIO44: PE_GPIO0 MXM Reset |
| 162 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44); |
| 163 | Data8 &= ~(UINT8)BIT6; |
| 164 | Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8); |
| 165 | Status = AGESA_SUCCESS; |
| 166 | } |
| 167 | // Travis |
| 168 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24); |
| 169 | Data8 &= ~(UINT8)BIT6 ; |
| 170 | Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8); |
| 171 | //Assert ALL PCIE RESET |
| 172 | // APU GPP0 (Dev 4) |
| 173 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); |
| 174 | Data8 &= ~(UINT8)BIT6; |
| 175 | Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); |
| 176 | // APU GPP1 (Dev 5) |
| 177 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01); |
| 178 | Data8 &= ~(UINT8)BIT6; |
| 179 | Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8); |
| 180 | // APU GPP2 (Dev 6) |
| 181 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00); |
| 182 | Data8 &= ~(UINT8)BIT6; |
| 183 | Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8); |
| 184 | // APU GPP3 (Dev 7) |
| 185 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27); |
| 186 | Data8 &= ~(UINT8)BIT6; |
| 187 | Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8); |
| 188 | } |
| 189 | return Status; |
| 190 | } |