Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
| 4 | # Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | # |
| 6 | # This program is free software; you can redistribute it and/or modify |
| 7 | # it under the terms of the GNU General Public License as published by |
| 8 | # the Free Software Foundation; version 2 of the License. |
| 9 | # |
| 10 | # This program is distributed in the hope that it will be useful, |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | # GNU General Public License for more details. |
| 14 | # |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 15 | chip northbridge/amd/agesa/family14/root_complex |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 16 | device cpu_cluster 0 on |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 17 | chip cpu/amd/agesa/family14 |
| 18 | device lapic 0 on end |
| 19 | end |
| 20 | end |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 21 | device domain 0 on |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 22 | subsystemid 0x1022 0x1510 inherit |
| 23 | chip northbridge/amd/agesa/family14 # CPU side of HT root complex |
| 24 | # device pci 18.0 on # northbridge |
| 25 | chip northbridge/amd/agesa/family14 # PCI side of HT root complex |
| 26 | device pci 0.0 on end # Root Complex |
Zheng Bao | 80adfdf | 2012-10-24 11:20:44 +0800 | [diff] [blame] | 27 | device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] |
Zheng Bao | 80adfdf | 2012-10-24 11:20:44 +0800 | [diff] [blame] | 28 | device pci 4.0 on end # PCIE P2P bridge on-board NIC |
| 29 | device pci 5.0 off end # PCIE P2P bridge |
| 30 | device pci 6.0 on end # PCIE P2P bridge PCIe slot |
| 31 | device pci 7.0 off end # PCIE P2P bridge |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 32 | device pci 8.0 off end # NB/SB Link P2P bridge |
| 33 | end # agesa northbridge |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 34 | |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 35 | chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus |
| 36 | device pci 11.0 on end # SATA |
Jens Rottmann | a48918f | 2013-02-20 21:12:37 +0100 | [diff] [blame] | 37 | device pci 12.0 on end # OHCI USB 0-4 |
| 38 | device pci 12.2 on end # EHCI USB 0-4 |
| 39 | device pci 13.0 on end # OHCI USB 5-9 |
| 40 | device pci 13.2 on end # EHCI USB 5-9 |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 41 | device pci 14.0 on # SM |
| 42 | chip drivers/generic/generic #dimm 0-0-0 |
| 43 | device i2c 50 on end |
| 44 | end |
| 45 | chip drivers/generic/generic #dimm 0-0-1 |
| 46 | device i2c 51 on end |
| 47 | end |
| 48 | end # SM |
| 49 | device pci 14.1 on end # IDE 0x439c |
| 50 | device pci 14.2 on end # HDA 0x4383 |
| 51 | device pci 14.3 on # LPC 0x439d |
| 52 | chip superio/fintek/f81865f |
| 53 | device pnp 4e.0 off # Floppy |
| 54 | io 0x60 = 0x3f0 |
| 55 | irq 0x70 = 6 |
| 56 | drq 0x74 = 2 |
| 57 | end |
| 58 | device pnp 4e.3 off end # Parallel Port |
| 59 | device pnp 4e.4 off end # Hardware Monitor |
| 60 | device pnp 4e.5 on # Keyboard |
| 61 | io 0x60 = 0x60 |
| 62 | io 0x62 = 0x64 |
| 63 | irq 0x70 = 1 |
| 64 | end |
| 65 | device pnp 4e.6 off end # GPIO |
| 66 | device pnp 4e.a off end # PME |
| 67 | device pnp 4e.10 on # COM1 |
| 68 | io 0x60 = 0x3f8 |
| 69 | irq 0x70 = 4 |
| 70 | end |
Dave Frodin | 3b19cba | 2013-02-08 13:16:58 -0700 | [diff] [blame] | 71 | device pnp 4e.11 on # COM2 |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 72 | io 0x60 = 0x2f8 |
| 73 | irq 0x70 = 3 |
| 74 | end |
| 75 | end # f81865f |
| 76 | end #LPC |
| 77 | device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} |
Jens Rottmann | a48918f | 2013-02-20 21:12:37 +0100 | [diff] [blame] | 78 | device pci 14.5 off end # OHCI FS/LS USB |
| 79 | device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 80 | device pci 15.0 off end # PCIe PortA |
| 81 | device pci 15.1 off end # PCIe PortB |
| 82 | device pci 15.2 off end # PCIe PortC |
| 83 | device pci 15.3 off end # PCIe PortD |
Jens Rottmann | a48918f | 2013-02-20 21:12:37 +0100 | [diff] [blame] | 84 | device pci 16.0 off end # OHCI USB 10-13 |
| 85 | device pci 16.2 off end # EHCI USB 10-13 |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 86 | register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) |
| 87 | register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 88 | |
| 89 | #set up SB800 Fan control registers and IMC fan controls |
| 90 | register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common |
| 91 | register "fan0_enabled" = "1" |
| 92 | register "fan1_enabled" = "1" |
| 93 | register "imc_fan_zone0_enabled" = "1" |
| 94 | register "imc_fan_zone1_enabled" = "1" |
| 95 | |
| 96 | register "fan0_config_vals" = "{ \ |
| 97 | FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ |
| 98 | FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\ |
| 99 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" |
| 100 | register "fan1_config_vals" = "{ \ |
| 101 | FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ |
| 102 | FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \ |
| 103 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" |
| 104 | |
| 105 | register "imc_zone0_mode1" = " \ |
| 106 | IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ |
| 107 | IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0" |
| 108 | register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ |
| 109 | IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED" |
| 110 | register "imc_zone0_temp_offset" = "0x00" # No temp offset |
| 111 | register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis |
| 112 | register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address |
| 113 | register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number |
| 114 | register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate |
| 115 | register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping |
| 116 | |
| 117 | register "imc_zone1_mode1" = " \ |
| 118 | IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ |
| 119 | IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1" |
| 120 | register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ |
| 121 | IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED" |
| 122 | register "imc_zone1_temp_offset" = "0x00" # No temp offset |
| 123 | register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis |
| 124 | register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address |
| 125 | register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number |
| 126 | register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate |
| 127 | register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping |
| 128 | |
| 129 | # T56N has a Maximum operating temperature of 90C |
| 130 | # ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C |
| 131 | # ZONEX_FANSPEEDS - Fan speeds as a "percentage" |
| 132 | register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }" |
| 133 | register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }" |
| 134 | register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }" |
| 135 | register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }" |
| 136 | |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 137 | end #southbridge/amd/cimx/sb800 |
| 138 | # end # device pci 18.0 |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 139 | # These seem unnecessary |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 140 | device pci 18.0 on end |
| 141 | device pci 18.1 on end |
| 142 | device pci 18.2 on end |
| 143 | device pci 18.3 on end |
| 144 | device pci 18.4 on end |
| 145 | device pci 18.5 on end |
| 146 | device pci 18.6 on end |
| 147 | device pci 18.7 on end |
Martin Roth | 45f72ce | 2013-02-24 12:58:33 -0700 | [diff] [blame] | 148 | |
| 149 | register "spdAddrLookup" = " |
| 150 | { |
| 151 | { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses |
| 152 | { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses |
| 153 | }" |
| 154 | |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 155 | end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 156 | end #domain |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 157 | end #northbridge/amd/agesa/family14/root_complex |