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review.coreboot.org / coreboot / 9631016660423d0585a1 / . / src / mainboard / amd / parmer / dsdt.asl
blob: a986ed50d2a0188af0089cdf75e457213ed023a6 [file] [log] [blame]
zbao323a9232012-07-19 16:39:01 +0800[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
Steve Goodrichbf0988b2013-07-10 11:59:11 -0600[diff] [blame]5 * Copyright (C) 2013 Sage Electronic Engineering, LLC
zbao323a9232012-07-19 16:39:01 +0800[diff] [blame]6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
zbao323a9232012-07-19 16:39:01 +0800[diff] [blame]15 */
16
17/* DefinitionBlock Statement */
18DefinitionBlock (
Steve Goodrichbf0988b2013-07-10 11:59:11 -0600[diff] [blame]19 "DSDT.AML", /* Output filename */
20 "DSDT", /* Signature */
21 0x02, /* DSDT Revision, needs to be 2 for 64bit */
22 "AMD ", /* OEMID */
23 "COREBOOT", /* TABLE ID */
24 0x00010001 /* OEM Revision */
zbao323a9232012-07-19 16:39:01 +0800[diff] [blame]25 )
26{ /* Start of ASL file */
Steve Goodrichbf0988b2013-07-10 11:59:11 -0600[diff] [blame]27 /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
zbao323a9232012-07-19 16:39:01 +0800[diff] [blame]28
Steve Goodrichbf0988b2013-07-10 11:59:11 -0600[diff] [blame]29 /* Globals for the platform */
30 #include "acpi/mainboard.asl"
zbao323a9232012-07-19 16:39:01 +0800[diff] [blame]31
Steve Goodrichbf0988b2013-07-10 11:59:11 -0600[diff] [blame]32 /* Describe the USB Overcurrent pins */
33 #include "acpi/usb_oc.asl"
zbao323a9232012-07-19 16:39:01 +0800[diff] [blame]34
Steve Goodrichbf0988b2013-07-10 11:59:11 -0600[diff] [blame]35 /* PCI IRQ mapping for the Southbridge */
36 #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
zbao323a9232012-07-19 16:39:01 +0800[diff] [blame]37
Steve Goodrichbf0988b2013-07-10 11:59:11 -0600[diff] [blame]38 /* Describe the processor tree (\_PR) */
39 #include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
zbao323a9232012-07-19 16:39:01 +0800[diff] [blame]40
Steve Goodrichbf0988b2013-07-10 11:59:11 -0600[diff] [blame]41 /* Describe the supported Sleep States for this Southbridge */
42 #include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
zbao323a9232012-07-19 16:39:01 +0800[diff] [blame]43
Steve Goodrichbf0988b2013-07-10 11:59:11 -0600[diff] [blame]44 /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
45 #include "acpi/sleep.asl"
Siyuan Wang03901122013-05-31 19:36:30 +0800[diff] [blame]46
zbao323a9232012-07-19 16:39:01 +0800[diff] [blame]47 Scope(\_SB) {
Steve Goodrichbf0988b2013-07-10 11:59:11 -0600[diff] [blame]48 /* global utility methods expected within the \_SB scope */
49 #include <arch/x86/acpi/globutil.asl>
50
51 /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
52 #include "acpi/routing.asl"
53
Alexandru Gagniuc44f2fab2014-04-18 01:42:19 -0500[diff] [blame]54 Device(PWRB) {
55 Name(_HID, EISAID("PNP0C0C"))
56 Name(_UID, 0xAA)
57 Name(_PRW, Package () {3, 0x04})
58 Name(_STA, 0x0B)
59 }
60
Steve Goodrichbf0988b2013-07-10 11:59:11 -0600[diff] [blame]61 Device(PCI0) {
62 /* Describe the AMD Northbridge */
63 #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
64
65 /* Describe the AMD Fusion Controller Hub Southbridge */
66 #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
67
zbao323a9232012-07-19 16:39:01 +0800[diff] [blame]68 }
69
Steve Goodrichbf0988b2013-07-10 11:59:11 -0600[diff] [blame]70 /* Describe PCI INT[A-H] for the Southbridge */
71 #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
zbao323a9232012-07-19 16:39:01 +0800[diff] [blame]72
73 } /* End Scope(_SB) */
74
Steve Goodrichbf0988b2013-07-10 11:59:11 -0600[diff] [blame]75 /* Describe SMBUS for the Southbridge */
76 #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
zbao323a9232012-07-19 16:39:01 +0800[diff] [blame]77
Steve Goodrichbf0988b2013-07-10 11:59:11 -0600[diff] [blame]78 /* Define the General Purpose Events for the platform */
79 #include "acpi/gpe.asl"
zbao323a9232012-07-19 16:39:01 +0800[diff] [blame]80
Steve Goodrichbf0988b2013-07-10 11:59:11 -0600[diff] [blame]81 /* Define the Thermal zones and methods for the platform */
82 #include "acpi/thermal.asl"
zbao323a9232012-07-19 16:39:01 +0800[diff] [blame]83
Steve Goodrichbf0988b2013-07-10 11:59:11 -0600[diff] [blame]84 /* Define the System Indicators for the platform */
85 #include "acpi/si.asl"
zbao323a9232012-07-19 16:39:01 +0800[diff] [blame]86
zbao323a9232012-07-19 16:39:01 +0800[diff] [blame]87}
88/* End of ASL file */