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review.coreboot.org / coreboot / 9631016660423d0585a1 / . / src / mainboard / amd / lamar / romstage.c
blob: bcf49e064edbc9da8c7975ae1ac7c5487d7363c8 [file] [log] [blame]
Bruce Griffith72645bb2014-06-10 05:10:19 -0600[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Bruce Griffith72645bb2014-06-10 05:10:19 -0600[diff] [blame]14 */
15
16#include <stdint.h>
17#include <string.h>
18#include <device/pci_def.h>
19#include <device/pci_ids.h>
20#include <arch/acpi.h>
21#include <arch/io.h>
22#include <arch/stages.h>
23#include <device/pnp_def.h>
24#include <arch/cpu.h>
25#include <cpu/x86/lapic.h>
26#include <console/console.h>
Aaron Durbindc9f5cd2015-09-08 13:34:43 -0500[diff] [blame]27#include <commonlib/loglevel.h>
Bruce Griffith72645bb2014-06-10 05:10:19 -0600[diff] [blame]28#include <cpu/amd/car.h>
29#include <northbridge/amd/pi/agesawrapper.h>
30#include <northbridge/amd/pi/agesawrapper_call.h>
31#include <cpu/x86/bist.h>
32#include <cpu/x86/lapic.h>
33#include <southbridge/amd/pi/hudson/hudson.h>
34#include <cpu/amd/pi/s3_resume.h>
35#include "cbmem.h"
36#include "superio/fintek/f81216h/f81216h.h"
37
38#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1)
39
40void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
41{
42 u32 val;
43
44 /*
45 * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
46 * LpcClk[1:0]". This following register setting has been
47 * replicated in every reference design since Parmer, so it is
48 * believed to be required even though it is not documented in
49 * the SoC BKDGs. Without this setting, there is no serial
50 * output.
51 */
52 outb(0xD2, 0xcd6);
53 outb(0x00, 0xcd7);
54
55 amd_initmmio();
56 hudson_lpc_decode();
57
58 outb(0x24, 0xCD6);
59 outb(0x01, 0xCD7);
60 *(volatile u32 *) (0xFED80000 + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */
61 *(volatile u32 *) (0xFED80000 + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */
62
63 hudson_lpc_port80();
64
65 if (!cpu_init_detectedx) {
66 post_code(0x30);
67 f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777);
68 post_code(0x31);
69 console_init();
70 }
71
72 /* Halt if there was a built in self test failure */
73 post_code(0x34);
74 report_bist_failure(bist);
75
76 /* Load MPB */
77 val = cpuid_eax(1);
78 printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
79 printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
80
81 post_code(0x37);
82 AGESAWRAPPER(amdinitreset);
83 post_code(0x38);
84 printk(BIOS_DEBUG, "Got past hudson_early_setup\n");
85
86 post_code(0x39);
87 AGESAWRAPPER(amdinitearly);
88 int s3resume = acpi_is_wakeup_s3();
89 if (!s3resume) {
90 post_code(0x40);
91 AGESAWRAPPER(amdinitpost);
92
93 post_code(0x41);
94 AGESAWRAPPER(amdinitenv);
95 /*
96 If code hangs here, please check cahaltasm.S
97 */
98 disable_cache_as_ram();
99 }
100 else if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { /* S3 detect */
101 printk(BIOS_INFO, "S3 detected\n");
102
103 post_code(0x60);
104 AGESAWRAPPER(amdinitresume);
105
106 AGESAWRAPPER(amds3laterestore);
107
108 post_code(0x61);
109 prepare_for_resume();
110 }
111
112 post_code(0x50);
113 copy_and_run();
114
115 post_code(0x54); /* Should never see this post code. */
116}