Bruce Griffith | 72645bb | 2014-06-10 05:10:19 -0600 | [diff] [blame] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
| 4 | # Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | # 2013 - 2014 Sage Electronic Engineering, LLC |
| 6 | # |
| 7 | # This program is free software; you can redistribute it and/or modify |
| 8 | # it under the terms of the GNU General Public License as published by |
| 9 | # the Free Software Foundation; version 2 of the License. |
| 10 | # |
| 11 | # This program is distributed in the hope that it will be useful, |
| 12 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | # GNU General Public License for more details. |
| 15 | # |
Bruce Griffith | 72645bb | 2014-06-10 05:10:19 -0600 | [diff] [blame] | 16 | chip northbridge/amd/pi/00630F01/root_complex |
| 17 | device cpu_cluster 0 on |
| 18 | chip cpu/amd/pi/00630F01 |
| 19 | device lapic 10 on end |
| 20 | end |
| 21 | end |
| 22 | |
| 23 | device domain 0 on |
| 24 | subsystemid 0x1022 0x1410 inherit |
| 25 | chip northbridge/amd/pi/00630F01 # CPU side of HT root complex |
| 26 | |
| 27 | chip northbridge/amd/pi/00630F01 # PCI side of HT root complex |
| 28 | device pci 0.0 on end # 0x1422 Root Complex |
| 29 | device pci 0.2 off end # 0x1423 IOMMU |
| 30 | device pci 1.0 on end # 0x13XX Internal Graphics |
| 31 | device pci 1.1 on end # 0x1308 DisplayPort/HDMI Audio |
| 32 | device pci 2.0 on end # 0x1424 GFX PCIe Host Bridge |
| 33 | device pci 2.1 on end # 0x1425 P2P Bridge for GFX PCIe Port 0 (PCIe x16 slot J119) |
| 34 | device pci 2.2 off end # 0x1425 P2P Bridge for GFX PCIe Port 1 |
| 35 | device pci 3.0 on end # 0x1424 GPP PCIe Host Bridge |
| 36 | device pci 3.1 on end # 0x1426 P2P Bridge for GPP PCIe Port 0 (PCIe x4 slot J118) |
| 37 | device pci 3.2 on end # 0x1426 P2P Bridge for GPP PCIe Port 1 (PCIe x4 slot J120) |
| 38 | device pci 3.3 off end # 0x1426 P2P Bridge for GPP PCIe Port 2 |
| 39 | device pci 3.4 off end # 0x1426 P2P Bridge for GPP PCIe Port 3 |
| 40 | device pci 3.5 off end # 0x1426 P2P Bridge for GPP PCIe Port 4 |
| 41 | device pci 4.0 on end # 0x1424 UMI PCIe Host Bridge |
| 42 | # device pci 4.1 on end # 0x1426 P2P bridge for UMI link |
| 43 | # device pci 4.2 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 3 |
| 44 | # device pci 4.3 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 2 |
| 45 | # device pci 4.4 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 1 |
| 46 | # device pci 4.5 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 0 |
| 47 | end #chip northbridge/amd/pi/00630F01 |
| 48 | |
| 49 | chip southbridge/amd/pi/hudson |
| 50 | device pci 10.0 on end # 0x7814 XHCI HC0 |
| 51 | device pci 10.1 on end # 0x7814 XHCI HC1 |
| 52 | device pci 11.0 on end # 0x7800-0x7805 SATA (device ID depends on mode) |
| 53 | device pci 12.0 on end # 0x7807 USB OHCI |
| 54 | device pci 12.2 on end # 0x7808 USB EHCI |
| 55 | device pci 13.0 on end # 0x7807 USB OHCI |
| 56 | device pci 13.2 on end # 0x7808 USB EHCI |
| 57 | device pci 14.0 on # 0x780B SMBus |
| 58 | chip drivers/generic/generic #dimm 0-0-0 |
| 59 | device i2c 50 on end |
| 60 | end |
| 61 | chip drivers/generic/generic #dimm 0-0-1 |
| 62 | device i2c 51 on end |
| 63 | end |
| 64 | chip drivers/generic/generic #dimm 0-1-0 |
| 65 | device i2c 52 on end |
| 66 | end |
| 67 | chip drivers/generic/generic #dimm 0-1-1 |
| 68 | device i2c 53 on end |
| 69 | end |
| 70 | end # SM |
| 71 | device pci 14.1 on end # 0x780C IDE |
| 72 | device pci 14.2 on end # 0x780D HDA |
| 73 | device pci 14.3 on # 0x780E LPC |
| 74 | chip superio/fintek/f81216h |
| 75 | register "conf_key_mode" = "0x77" |
| 76 | device pnp 4e.0 on # COM1 |
| 77 | io 0x60 = 0x3f8 |
| 78 | irq 0x70 = 4 |
| 79 | end |
| 80 | device pnp 4e.1 on # COM2 |
| 81 | io 0x60 = 0x2f8 |
| 82 | irq 0x70 = 3 |
| 83 | end |
| 84 | device pnp 4e.2 off end # COM3 |
| 85 | device pnp 4e.3 off end # COM4 |
| 86 | device pnp 4e.8 off end # WDT |
| 87 | end # f81865f |
| 88 | end #LPC |
| 89 | device pci 14.4 on end # 0x780F PCI :: PCI-b conflict with GPIO. |
| 90 | device pci 14.5 on end # 0x7809 USB OHCI |
| 91 | device pci 14.7 on end # 0x7806 SD Flash Controller |
| 92 | device pci 15.0 on end # 0x43A0 SB GPP Port 0 (Integrated Realtek GbE Controller) |
| 93 | device pci 15.1 on end # 0x43A1 SB GPP Port 1 (mPCIe slot J122) |
| 94 | device pci 15.2 on end # 0x43A2 SB GPP Port 2 (mPCIe slot J123) |
| 95 | device pci 15.3 off end # 0x43A3 SB GPP Port 3 |
| 96 | register "gpp_configuration" = "4" |
| 97 | device pci 16.0 on end # 0x7809 USB OHCI (when the xHCI device is disabled) |
| 98 | end #southbridge/amd/pi/hudson |
| 99 | |
| 100 | device pci 18.0 on end # 0x141A HT Configuration |
| 101 | device pci 18.1 on end # 0x141B Address Maps |
| 102 | device pci 18.2 on end # 0x141C DRAM Configuration |
| 103 | device pci 18.3 on end # 0x141D Miscellaneous |
| 104 | device pci 18.4 on end # 0x141E Power Management |
| 105 | device pci 18.5 on end # 0x141F Northbridge |
| 106 | |
| 107 | register "spdAddrLookup" = " |
| 108 | { |
| 109 | { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses |
| 110 | }" |
| 111 | |
| 112 | end #chip northbridge/amd/pi/00630F01 # CPU side of HT root complex |
| 113 | end #domain |
| 114 | end #northbridge/amd/pi/00630F01/root_complex |