Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <device/device.h> |
| 18 | #include <device/pci.h> |
| 19 | #include <arch/io.h> |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 20 | #include <cpu/x86/msr.h> |
| 21 | #include <cpu/amd/mtrr.h> |
| 22 | #include <device/pci_def.h> |
Kimarie Hoot | 31c5e07 | 2013-03-06 16:18:09 -0700 | [diff] [blame] | 23 | #include <southbridge/amd/sb800/sb800.h> |
Kerry Sheh | 19329c9 | 2012-01-19 13:18:36 +0800 | [diff] [blame] | 24 | #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 25 | |
Jens Rottmann | 27a1be9 | 2013-04-03 10:12:55 +0200 | [diff] [blame] | 26 | void broadcom_init(void); |
Kerry Sheh | 01f7ab9 | 2012-01-19 13:18:36 +0800 | [diff] [blame] | 27 | void set_pcie_reset(void); |
| 28 | void set_pcie_dereset(void); |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 29 | |
| 30 | /** |
| 31 | * TODO |
| 32 | * SB CIMx callback |
| 33 | */ |
| 34 | void set_pcie_reset(void) |
| 35 | { |
| 36 | } |
| 37 | |
| 38 | /** |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 39 | * mainboard specific SB CIMx callback |
| 40 | */ |
| 41 | void set_pcie_dereset(void) |
| 42 | { |
Kerry Sheh | 19329c9 | 2012-01-19 13:18:36 +0800 | [diff] [blame] | 43 | /** |
| 44 | * GPIO32 Pcie Device DeAssert for APU |
| 45 | * GPIO25 Pcie LAN, APU GPP2 |
| 46 | * GPIO02 MINIPCIE SLOT1, APU GPP3 |
| 47 | * GPIO50 Pcie Device DeAssert for Hudson Southbridge |
| 48 | * GPIO05 Express Card, SB GPP0 |
| 49 | * GPIO26 NEC USB3.0GPPUSB, SB GPP1 |
| 50 | * GPIO00 MINIPCIE SLOT2, SB GPP2 |
| 51 | * GPIO05 Pcie X1 Slot, SB GPP3 |
| 52 | */ |
| 53 | |
| 54 | /* Multi-function pins switch to GPIO0-35, these pins are shared with |
| 55 | * PCI pins, make sure Husson PCI device is disabled. |
| 56 | */ |
| 57 | RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1); |
| 58 | |
| 59 | /* select IOMux to function1/2, corresponds to GPIO */ |
| 60 | RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG32, AccWidthUint8, ~(BIT0 | BIT1), 1); |
| 61 | RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG50, AccWidthUint8, ~(BIT0 | BIT1), 2); |
| 62 | |
| 63 | |
| 64 | /* output low */ |
| 65 | RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG32, AccWidthUint8, ~(0xFF), 0x48); |
| 66 | RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG50, AccWidthUint8, ~(0xFF), 0x48); |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 67 | } |
| 68 | |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 69 | |
Jens Rottmann | 5e70766 | 2013-02-26 15:56:11 +0100 | [diff] [blame] | 70 | /********************************************** |
| 71 | * Enable the dedicated functions of the board. |
| 72 | **********************************************/ |
Paul Menzel | 528640d | 2013-02-23 21:31:23 +0100 | [diff] [blame] | 73 | static void mainboard_enable(device_t dev) |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 74 | { |
Kerry Sheh | 01f7ab9 | 2012-01-19 13:18:36 +0800 | [diff] [blame] | 75 | printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); |
| 76 | |
Kerry Sheh | 19329c9 | 2012-01-19 13:18:36 +0800 | [diff] [blame] | 77 | /* Inagua mainboard specific setting */ |
| 78 | set_pcie_dereset(); |
Kimarie Hoot | 31c5e07 | 2013-03-06 16:18:09 -0700 | [diff] [blame] | 79 | |
| 80 | /* |
| 81 | * Initialize ASF registers to an arbitrary address because someone |
| 82 | * long ago set things up this way inside the SPD read code. The |
| 83 | * SPD read code has been made generic and moved out of the board |
| 84 | * directory, so the ASF init is being done here. |
| 85 | */ |
| 86 | pm_iowrite(0x29, 0x80); |
| 87 | pm_iowrite(0x28, 0x61); |
Jens Rottmann | 3926b4c | 2013-03-01 19:41:41 +0100 | [diff] [blame] | 88 | |
| 89 | /* Upload AMD A55E GbE 'NV'RAM contents. Still untested on Inagua. |
| 90 | * After anyone can confirm it works please uncomment the call. */ |
| 91 | //broadcom_init(); |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 92 | } |
| 93 | |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 94 | struct chip_operations mainboard_ops = { |
Jens Rottmann | 5e70766 | 2013-02-26 15:56:11 +0100 | [diff] [blame] | 95 | .enable_dev = mainboard_enable, |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 96 | }; |