blob: ce1a893f933efb2fdd083a25aa7477d4b4b11f0a [file] [log] [blame]
Frank Vibrans69da1b62011-02-14 19:04:45 +00001#
2# This file is part of the coreboot project.
3#
4# Copyright (C) 2011 Advanced Micro Devices, Inc.
5#
6# This program is free software; you can redistribute it and/or modify
7# it under the terms of the GNU General Public License as published by
8# the Free Software Foundation; version 2 of the License.
9#
10# This program is distributed in the hope that it will be useful,
11# but WITHOUT ANY WARRANTY; without even the implied warranty of
12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13# GNU General Public License for more details.
14#
efdesign9805a89ab2011-06-20 17:38:49 -070015chip northbridge/amd/agesa/family14/root_complex
Stefan Reinauer0aa37c42013-02-12 15:20:54 -080016 device cpu_cluster 0 on
Kerry Shehf03360f2012-01-19 13:25:55 +080017 chip cpu/amd/agesa/family14
18 device lapic 0 on end
19 end
20 end
Stefan Reinauer4aff4452013-02-12 14:17:15 -080021 device domain 0 on
Kerry Shehf03360f2012-01-19 13:25:55 +080022 subsystemid 0x1022 0x1510 inherit
23 chip northbridge/amd/agesa/family14 # CPU side of HT root complex
24# device pci 18.0 on # northbridge
25 chip northbridge/amd/agesa/family14 # PCI side of HT root complex
26 device pci 0.0 on end # Root Complex
27 device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806
Jens Rottmannfc148742013-02-27 15:21:21 +010028 device pci 1.1 on end # Internal HDMI Audio
Kerry Shehf03360f2012-01-19 13:25:55 +080029 device pci 4.0 on end # PCIE P2P bridge MXM lane 0
30 device pci 5.0 off end # PCIE P2P bridge MXM lane 1
31 device pci 6.0 on end # PCIE P2P bridge LAN
32 device pci 7.0 on end # PCIE P2P bridge MINIPCIE SLOT1
33 device pci 8.0 off end # NB/SB Link P2P bridge
34 end # agesa northbridge
Frank Vibrans69da1b62011-02-14 19:04:45 +000035
Kerry Shehf03360f2012-01-19 13:25:55 +080036 chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
37 device pci 11.0 on end # SATA
Jens Rottmanna48918f2013-02-20 21:12:37 +010038 device pci 12.0 on end # OHCI USB 0-4
39 device pci 12.2 on end # EHCI USB 0-4
40 device pci 13.0 on end # OHCI USB 5-9
41 device pci 13.2 on end # EHCI USB 5-9
Kerry Shehf03360f2012-01-19 13:25:55 +080042 device pci 14.0 on # SM
43 chip drivers/generic/generic #dimm 0-0-0
44 device i2c 50 on end
45 end
46 chip drivers/generic/generic #dimm 0-0-1
47 device i2c 51 on end
48 end
49 end # SM
50 device pci 14.1 on end # IDE 0x439c
51 device pci 14.2 on end # HDA 0x4383
52 device pci 14.3 on # LPC 0x439d
53 chip superio/smsc/kbc1100
54 device pnp 2e.7 on # Keyboard
55 io 0x60 = 0x60
56 io 0x62 = 0x64
57 irq 0x70 = 1
58 irq 0x72 = 12
59 end
60 end # kbc1100
Frank Vibrans69da1b62011-02-14 19:04:45 +000061 end #LPC
Kerry Sheh01f7ab92012-01-19 13:18:36 +080062 device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
Jens Rottmanna48918f2013-02-20 21:12:37 +010063 device pci 14.5 on end # OHCI FS/LS USB
64 device pci 14.6 on end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
Kerry Sheh9e83175d2012-01-19 13:18:37 +080065 device pci 15.0 on end # PCIe PortA Express Card
66 device pci 15.1 on end # PCIe PortB NEC USB3.0
67 device pci 15.2 on end # PCIe PortC MINIPCIE SLOT2
68 device pci 15.3 on end # PCIe PortD PCIE X1 SLOT
Jens Rottmanna48918f2013-02-20 21:12:37 +010069 device pci 16.0 on end # OHCI USB 10-13
70 device pci 16.2 on end # EHCI USB 10-13
Frank Vibrans69da1b62011-02-14 19:04:45 +000071 register "gpp_configuration" = "4" #1:1:1:1
Kerry Shehf03360f2012-01-19 13:25:55 +080072 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
efdesign9805a89ab2011-06-20 17:38:49 -070073 end #southbridge/amd/cimx/sb800
Kerry Shehf03360f2012-01-19 13:25:55 +080074# end # device pci 18.0
Frank Vibrans69da1b62011-02-14 19:04:45 +000075# These seem unnecessary
Kerry Shehf03360f2012-01-19 13:25:55 +080076 device pci 18.0 on end
77 #device pci 18.0 on end
78 device pci 18.1 on end
79 device pci 18.2 on end
80 device pci 18.3 on end
81 device pci 18.4 on end
82 device pci 18.5 on end
83 device pci 18.6 on end
84 device pci 18.7 on end
Kimarie Hoot31c5e072013-03-06 16:18:09 -070085
86 register "spdAddrLookup" = "
87 {
88 { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
89 }"
Kerry Shehf03360f2012-01-19 13:25:55 +080090 end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
Stefan Reinauer4aff4452013-02-12 14:17:15 -080091 end #domain
efdesign9805a89ab2011-06-20 17:38:49 -070092end #northbridge/amd/agesa/family14/root_complex