Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 16 | #include "PlatformGnbPcieComplex.h" |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 17 | |
Edward O'Callaghan | 8864e1c | 2014-04-30 23:13:08 +1000 | [diff] [blame] | 18 | #include <string.h> |
Kyösti Mälkki | 34ad72c | 2014-10-21 13:43:46 +0300 | [diff] [blame] | 19 | #include <northbridge/amd/agesa/agesawrapper.h> |
Edward O'Callaghan | d63b97f | 2014-06-12 16:12:43 +1000 | [diff] [blame] | 20 | #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> |
Edward O'Callaghan | 8864e1c | 2014-04-30 23:13:08 +1000 | [diff] [blame] | 21 | |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 22 | #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE |
| 23 | |
Kerry Sheh | 01f7ab9 | 2012-01-19 13:18:36 +0800 | [diff] [blame] | 24 | /*---------------------------------------------------------------------------------------*/ |
| 25 | /** |
| 26 | * OemCustomizeInitEarly |
| 27 | * |
| 28 | * Description: |
Paul Menzel | 63950f8 | 2013-02-01 23:51:40 +0100 | [diff] [blame] | 29 | * This stub function will call the host environment through the binary block |
Kerry Sheh | 01f7ab9 | 2012-01-19 13:18:36 +0800 | [diff] [blame] | 30 | * interface (call-out port) to provide a user hook opportunity |
| 31 | * |
| 32 | * Parameters: |
Kerry Sheh | 01f7ab9 | 2012-01-19 13:18:36 +0800 | [diff] [blame] | 33 | * @param[in] *InitEarly |
| 34 | * |
| 35 | * @retval VOID |
| 36 | * |
| 37 | **/ |
| 38 | /*---------------------------------------------------------------------------------------*/ |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 39 | |
| 40 | static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) |
Kerry Sheh | 01f7ab9 | 2012-01-19 13:18:36 +0800 | [diff] [blame] | 41 | { |
| 42 | AGESA_STATUS Status; |
| 43 | VOID *BrazosPcieComplexListPtr; |
| 44 | VOID *BrazosPciePortPtr; |
| 45 | VOID *BrazosPcieDdiPtr; |
| 46 | |
| 47 | ALLOCATE_HEAP_PARAMS AllocHeapParams; |
| 48 | |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 49 | PCIe_PORT_DESCRIPTOR PortList [] = { |
| 50 | // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM |
| 51 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 52 | 0, |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 53 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5), |
| 54 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) |
| 55 | }, |
| 56 | // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN |
| 57 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 58 | 0, |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 59 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), |
| 60 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) |
| 61 | }, |
| 62 | // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1 |
| 63 | { |
| 64 | 0, |
| 65 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), |
| 66 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) |
| 67 | }, |
| 68 | // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) |
| 69 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 70 | DESCRIPTOR_TERMINATE_LIST, |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 71 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), |
| 72 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) |
| 73 | } |
| 74 | }; |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 75 | |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 76 | PCIe_DDI_DESCRIPTOR DdiList [] = { |
| 77 | // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS |
| 78 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 79 | 0, |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 80 | PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), |
| 81 | PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1) |
| 82 | }, |
| 83 | // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA |
| 84 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 85 | DESCRIPTOR_TERMINATE_LIST, |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 86 | PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), |
| 87 | PCIE_DDI_DATA_INITIALIZER (ConnectorTypeAutoDetect, Aux2, Hdp2) |
| 88 | } |
| 89 | }; |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 90 | |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 91 | PCIe_COMPLEX_DESCRIPTOR Brazos = { |
| 92 | DESCRIPTOR_TERMINATE_LIST, |
| 93 | 0, |
| 94 | &PortList[0], |
| 95 | &DdiList[0] |
| 96 | }; |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 97 | |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 98 | // GNB PCIe topology Porting |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 99 | |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 100 | // |
| 101 | // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR |
| 102 | // |
Paul Menzel | d189229 | 2013-05-14 10:06:47 +0200 | [diff] [blame] | 103 | AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 104 | |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 105 | AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; |
| 106 | AllocHeapParams.Persist = HEAP_LOCAL_CACHE; |
| 107 | Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); |
Kyösti Mälkki | 1ef67e1 | 2014-12-16 16:45:52 +0200 | [diff] [blame] | 108 | ASSERT(Status == AGESA_SUCCESS); |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 109 | |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 110 | BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 111 | |
Paul Menzel | d189229 | 2013-05-14 10:06:47 +0200 | [diff] [blame] | 112 | AllocHeapParams.BufferPtr += sizeof(Brazos); |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 113 | BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 114 | |
Paul Menzel | d189229 | 2013-05-14 10:06:47 +0200 | [diff] [blame] | 115 | AllocHeapParams.BufferPtr += sizeof(PortList); |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 116 | BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 117 | |
Edward O'Callaghan | 8864e1c | 2014-04-30 23:13:08 +1000 | [diff] [blame] | 118 | memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); |
| 119 | memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); |
| 120 | memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 121 | |
| 122 | |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 123 | ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; |
| 124 | ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 125 | |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 126 | InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; |
| 127 | InitEarly->GnbConfig.PsppPolicy = 0; |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 128 | return AGESA_SUCCESS; |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 129 | } |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 130 | |
| 131 | const struct OEM_HOOK OemCustomize = { |
| 132 | .InitEarly = OemInitEarly, |
| 133 | }; |