Kerry Sheh | 6d6d18e | 2012-02-07 20:32:34 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Kerry Sheh | 6d6d18e | 2012-02-07 20:32:34 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #ifndef _RD890_CFG_H_ |
| 17 | #define _RD890_CFG_H_ |
| 18 | |
| 19 | #include "NbPlatform.h" |
| 20 | |
| 21 | #define RD890_IOAPIC_ADDR 0xC8000000 |
| 22 | /* platform dependent configuration default value */ |
| 23 | |
| 24 | /** |
| 25 | * Path from CPU to NB |
| 26 | * [0..7] - Node (0..8) |
| 27 | * [8..11] - Link (0..3) |
| 28 | * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. |
| 29 | */ |
| 30 | #ifndef DEFAULT_HT_PATH |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 31 | #if CONFIG_CPU_AMD_AGESA_FAMILY10 |
Kerry Sheh | 6d6d18e | 2012-02-07 20:32:34 +0800 | [diff] [blame] | 32 | #define DEFAULT_HT_PATH {0x0, 0x3} |
| 33 | #endif |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 34 | #if CONFIG_CPU_AMD_AGESA_FAMILY15 |
Kerry Sheh | 6d6d18e | 2012-02-07 20:32:34 +0800 | [diff] [blame] | 35 | #define DEFAULT_HT_PATH {0x0, 0x1} |
| 36 | #endif |
| 37 | #endif |
| 38 | |
| 39 | /** |
| 40 | * Bitmap of enabled ports on NB #0/1/2/3 |
| 41 | * Bit[0] - Reserved |
| 42 | * Bit[1] - Reserved |
| 43 | * Bit[2] - Enable PCIe port 2 |
| 44 | * Bit[3] - Enable PCIe port 3 |
| 45 | * Bit[4] - Enable PCIe port 4 |
| 46 | * Bit[5] - Enable PCIe port 5 |
| 47 | * Bit[6] - Enable PCIe port 2 |
| 48 | * Bit[7] - Enable PCIe port 7 |
| 49 | * Bit[8] - Reserved |
| 50 | * Bit[9] - Enable PCIe port 9 |
| 51 | * Bit[10]- Enable PCIe port 10 |
| 52 | * Bit[11]- Enable PCIe port 11 |
| 53 | * Bit[12]- Enable PCIe port 12 |
| 54 | * Bit[13]- Enable PCIe port 13 |
| 55 | * Example: |
| 56 | * port_enable = 0x14 |
| 57 | * Port 2 and 4 enabled for training/initialization |
| 58 | */ |
| 59 | #ifndef DEFAULT_PORT_ENABLE_MAP |
| 60 | #define DEFAULT_PORT_ENABLE_MAP 0x0014 |
| 61 | #endif |
| 62 | |
| 63 | /** |
| 64 | * Bitmap of ports that have slot or onboard device connected. |
| 65 | * Example force PCIe Gen1 supporton port 2 and 4 (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4) |
Martin Roth | d30746ab6 | 2015-01-04 15:29:08 -0700 | [diff] [blame] | 66 | * define DEFAULT_PORT_FORCE_GEN1 0x604 |
Kerry Sheh | 6d6d18e | 2012-02-07 20:32:34 +0800 | [diff] [blame] | 67 | */ |
| 68 | #ifndef DEFAULT_PORT_FORCE_GEN1 |
| 69 | #define DEFAULT_PORT_FORCE_GEN1 0x0 |
| 70 | #endif |
| 71 | |
| 72 | /** |
| 73 | * Bitmap of ports that have server hotplug support |
| 74 | */ |
| 75 | #ifndef DEFAULT_HOTPLUG_SUPPORT |
| 76 | #define DEFAULT_HOTPLUG_SUPPORT 0x0 |
| 77 | #endif |
| 78 | |
| 79 | #ifndef DEFAULT_HOTPLUG_DESCRIPTOR |
| 80 | #define DEFAULT_HOTPLUG_DESCRIPTOR {0, 0, 0, 0, 0, 0, 0, 0} |
| 81 | #endif |
| 82 | |
| 83 | #ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS |
| 84 | #define DEFAULT_TEMPMMIO_BASE_ADDRESS 0xD0000000 |
| 85 | #endif |
| 86 | |
| 87 | /** |
| 88 | * Default GPP1 core configuraton on NB #0/1/2/3. |
| 89 | * 2 x8 slot, GFX_CONFIG_AABB |
| 90 | * 1 x16 slot, GFX_CONFIG_AAAA |
| 91 | */ |
| 92 | #ifndef DEFAULT_GPP1_CONFIG |
| 93 | #define DEFAULT_GPP1_CONFIG GFX_CONFIG_AABB |
| 94 | #endif |
| 95 | |
| 96 | /** |
| 97 | * Default GPP2 core configuraton on NB #0/1/2/3. |
| 98 | * 2 x8 slot, GFX_CONFIG_AABB |
| 99 | * 1 x16 slot, GFX_CONFIG_AAAA |
| 100 | */ |
| 101 | #ifndef DEFAULT_GPP2_CONFIG |
| 102 | #define DEFAULT_GPP2_CONFIG GFX_CONFIG_AABB |
| 103 | #endif |
| 104 | |
| 105 | /** |
| 106 | * Default GPP3a core configuraton on NB #0/1/2/3. |
| 107 | * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1 |
| 108 | * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2 |
| 109 | * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3 |
| 110 | * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4 |
| 111 | * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5 |
| 112 | * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6 |
| 113 | */ |
| 114 | #ifndef DEFAULT_GPP3A_CONFIG |
| 115 | #define DEFAULT_GPP3A_CONFIG GPP_CONFIG_GPP111111 |
| 116 | #endif |
| 117 | |
| 118 | |
| 119 | /** |
| 120 | * Default HT Transmitter de-emphasis setting |
| 121 | */ |
| 122 | #ifndef DEFAULT_HT_DEEMPASIES |
| 123 | #define DEFAULT_HT_DEEMPASIES 0x3 |
| 124 | #endif |
| 125 | |
| 126 | /** |
| 127 | * Default APIC nterrupt base for IOAPIC |
| 128 | */ |
| 129 | #ifndef DEFAULT_APIC_INTERRUPT_BASE |
| 130 | #define DEFAULT_APIC_INTERRUPT_BASE 24 |
| 131 | #endif |
| 132 | |
| 133 | |
| 134 | #define DEFAULT_PLATFORM_CONFIG(name) \ |
| 135 | NB_PLATFORM_CONFIG name = { \ |
| 136 | DEFAULT_PORT_ENABLE_MAP, \ |
| 137 | DEFAULT_PORT_FORCE_GEN1, \ |
| 138 | DEFAULT_HOTPLUG_SUPPORT, \ |
| 139 | DEFAULT_HOTPLUG_DESCRIPTOR, \ |
| 140 | DEFAULT_TEMPMMIO_BASE_ADDRESS, \ |
| 141 | DEFAULT_GPP1_CONFIG, \ |
| 142 | DEFAULT_GPP2_CONFIG, \ |
| 143 | DEFAULT_GPP3A_CONFIG, \ |
| 144 | DEFAULT_HT_DEEMPASIES, \ |
| 145 | /*DEFAULT_HT_PATH,*/ \ |
| 146 | DEFAULT_APIC_INTERRUPT_BASE, \ |
| 147 | } |
| 148 | |
| 149 | /** |
| 150 | * Platform configuration |
| 151 | */ |
| 152 | typedef struct { |
| 153 | UINT16 PortEnableMap; ///< Bitmap of enabled ports |
| 154 | UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 |
| 155 | UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug |
| 156 | UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors |
| 157 | UINT32 TemporaryMmio; ///< Temporary MMIO |
| 158 | UINT32 Gpp1Config; ///< Default PCIe GFX core configuration |
| 159 | UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration |
| 160 | UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration |
| 161 | UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level |
| 162 | // HT_PATH NbHtPath; ///< HT path to NB |
| 163 | UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. |
| 164 | } NB_PLATFORM_CONFIG; |
| 165 | |
| 166 | /** |
| 167 | * Bridge CIMx configuration |
| 168 | */ |
| 169 | void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig); |
| 170 | |
| 171 | #endif //_RD890_CFG_H_ |