Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | /* DefinitionBlock Statement */ |
| 17 | DefinitionBlock ( |
| 18 | "DSDT.AML", /* Output filename */ |
| 19 | "DSDT", /* Signature */ |
| 20 | 0x02, /* DSDT Revision, needs to be 2 for 64bit */ |
| 21 | "AMD ", /* OEMID */ |
Paul Menzel | 12d6024 | 2013-02-21 15:54:50 +0100 | [diff] [blame] | 22 | "COREBOOT", /* TABLE ID */ |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 23 | 0x00010001 /* OEM Revision */ |
| 24 | ) |
| 25 | { /* Start of ASL file */ |
Patrick Georgi | 91bd306 | 2012-02-16 19:16:14 +0100 | [diff] [blame] | 26 | /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 27 | |
| 28 | /* Data to be patched by the BIOS during POST */ |
| 29 | /* FIXME the patching is not done yet! */ |
| 30 | /* Memory related values */ |
| 31 | Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ |
| 32 | Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ |
| 33 | Name(PBLN, 0x0) /* Length of BIOS area */ |
| 34 | |
| 35 | Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ |
| 36 | Name(HPBA, 0xFED00000) /* Base address of HPET table */ |
| 37 | |
| 38 | Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ |
| 39 | |
| 40 | /* USB overcurrent mapping pins. */ |
| 41 | Name(UOM0, 0) |
| 42 | Name(UOM1, 2) |
| 43 | Name(UOM2, 0) |
| 44 | Name(UOM3, 7) |
| 45 | Name(UOM4, 2) |
| 46 | Name(UOM5, 2) |
| 47 | Name(UOM6, 6) |
| 48 | Name(UOM7, 2) |
| 49 | Name(UOM8, 6) |
| 50 | Name(UOM9, 6) |
| 51 | |
| 52 | /* Some global data */ |
Edward O'Callaghan | f7d8f09 | 2014-05-31 13:57:52 +1000 | [diff] [blame] | 53 | Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 54 | Name(OSV, Ones) /* Assume nothing */ |
| 55 | Name(PMOD, One) /* Assume APIC */ |
| 56 | |
| 57 | /* |
| 58 | * Processor Object |
| 59 | * |
| 60 | */ |
| 61 | Scope (\_PR) { /* define processor scope */ |
| 62 | Processor( |
| 63 | CPU0, /* name space name */ |
| 64 | 0, /* Unique number for this processor */ |
| 65 | 0x808, /* PBLK system I/O address !hardcoded! */ |
| 66 | 0x06 /* PBLKLEN for boot processor */ |
| 67 | ) { |
| 68 | #include "acpi/cpstate.asl" |
| 69 | } |
| 70 | |
| 71 | Processor( |
| 72 | CPU1, /* name space name */ |
| 73 | 1, /* Unique number for this processor */ |
| 74 | 0x0000, /* PBLK system I/O address !hardcoded! */ |
| 75 | 0x00 /* PBLKLEN for boot processor */ |
| 76 | ) { |
| 77 | #include "acpi/cpstate.asl" |
| 78 | } |
| 79 | |
| 80 | Processor( |
| 81 | CPU2, /* name space name */ |
| 82 | 2, /* Unique number for this processor */ |
| 83 | 0x0000, /* PBLK system I/O address !hardcoded! */ |
| 84 | 0x00 /* PBLKLEN for boot processor */ |
| 85 | ) { |
| 86 | #include "acpi/cpstate.asl" |
| 87 | } |
| 88 | |
| 89 | Processor( |
| 90 | CPU3, /* name space name */ |
| 91 | 3, /* Unique number for this processor */ |
| 92 | 0x0000, /* PBLK system I/O address !hardcoded! */ |
| 93 | 0x00 /* PBLKLEN for boot processor */ |
| 94 | ) { |
| 95 | #include "acpi/cpstate.asl" |
| 96 | } |
| 97 | } /* End _PR scope */ |
| 98 | |
| 99 | /* PIC IRQ mapping registers, C00h-C01h. */ |
| 100 | OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) |
| 101 | Field(PRQM, ByteAcc, NoLock, Preserve) { |
| 102 | PRQI, 0x00000008, |
| 103 | PRQD, 0x00000008, /* Offset: 1h */ |
| 104 | } |
| 105 | IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { |
| 106 | PIRA, 0x00000008, /* Index 0 */ |
| 107 | PIRB, 0x00000008, /* Index 1 */ |
| 108 | PIRC, 0x00000008, /* Index 2 */ |
| 109 | PIRD, 0x00000008, /* Index 3 */ |
| 110 | PIRE, 0x00000008, /* Index 4 */ |
| 111 | PIRF, 0x00000008, /* Index 5 */ |
| 112 | PIRG, 0x00000008, /* Index 6 */ |
| 113 | PIRH, 0x00000008, /* Index 7 */ |
| 114 | } |
| 115 | |
| 116 | /* PCI Error control register */ |
| 117 | OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) |
| 118 | Field(PERC, ByteAcc, NoLock, Preserve) { |
| 119 | SENS, 0x00000001, |
| 120 | PENS, 0x00000001, |
| 121 | SENE, 0x00000001, |
| 122 | PENE, 0x00000001, |
| 123 | } |
| 124 | |
| 125 | /* Client Management index/data registers */ |
| 126 | OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) |
| 127 | Field(CMT, ByteAcc, NoLock, Preserve) { |
| 128 | CMTI, 8, |
| 129 | /* Client Management Data register */ |
| 130 | G64E, 1, |
| 131 | G64O, 1, |
| 132 | G32O, 2, |
| 133 | , 2, |
| 134 | GPSL, 2, |
| 135 | } |
| 136 | |
| 137 | /* GPM Port register */ |
| 138 | OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) |
| 139 | Field(GPT, ByteAcc, NoLock, Preserve) { |
| 140 | GPB0,1, |
| 141 | GPB1,1, |
| 142 | GPB2,1, |
| 143 | GPB3,1, |
| 144 | GPB4,1, |
| 145 | GPB5,1, |
| 146 | GPB6,1, |
| 147 | GPB7,1, |
| 148 | } |
| 149 | |
| 150 | /* Flash ROM program enable register */ |
| 151 | OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) |
| 152 | Field(FRE, ByteAcc, NoLock, Preserve) { |
| 153 | , 0x00000006, |
| 154 | FLRE, 0x00000001, |
| 155 | } |
| 156 | |
| 157 | /* PM2 index/data registers */ |
| 158 | OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) |
| 159 | Field(PM2R, ByteAcc, NoLock, Preserve) { |
| 160 | PM2I, 0x00000008, |
| 161 | PM2D, 0x00000008, |
| 162 | } |
| 163 | |
| 164 | /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ |
| 165 | OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) |
| 166 | Field(PIOR, ByteAcc, NoLock, Preserve) { |
| 167 | PIOI, 0x00000008, |
| 168 | PIOD, 0x00000008, |
| 169 | } |
| 170 | IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { |
| 171 | Offset(0x00), /* MiscControl */ |
| 172 | , 1, |
| 173 | T1EE, 1, |
| 174 | T2EE, 1, |
| 175 | Offset(0x01), /* MiscStatus */ |
| 176 | , 1, |
| 177 | T1E, 1, |
| 178 | T2E, 1, |
| 179 | Offset(0x04), /* SmiWakeUpEventEnable3 */ |
| 180 | , 7, |
| 181 | SSEN, 1, |
| 182 | Offset(0x07), /* SmiWakeUpEventStatus3 */ |
| 183 | , 7, |
| 184 | CSSM, 1, |
| 185 | Offset(0x10), /* AcpiEnable */ |
| 186 | , 6, |
| 187 | PWDE, 1, |
| 188 | Offset(0x1C), /* ProgramIoEnable */ |
| 189 | , 3, |
| 190 | MKME, 1, |
| 191 | IO3E, 1, |
| 192 | IO2E, 1, |
| 193 | IO1E, 1, |
| 194 | IO0E, 1, |
| 195 | Offset(0x1D), /* IOMonitorStatus */ |
| 196 | , 3, |
| 197 | MKMS, 1, |
| 198 | IO3S, 1, |
| 199 | IO2S, 1, |
| 200 | IO1S, 1, |
| 201 | IO0S,1, |
| 202 | Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */ |
| 203 | APEB, 16, |
| 204 | Offset(0x36), /* GEvtLevelConfig */ |
| 205 | , 6, |
| 206 | ELC6, 1, |
| 207 | ELC7, 1, |
| 208 | Offset(0x37), /* GPMLevelConfig0 */ |
| 209 | , 3, |
| 210 | PLC0, 1, |
| 211 | PLC1, 1, |
| 212 | PLC2, 1, |
| 213 | PLC3, 1, |
| 214 | PLC8, 1, |
| 215 | Offset(0x38), /* GPMLevelConfig1 */ |
| 216 | , 1, |
| 217 | PLC4, 1, |
| 218 | PLC5, 1, |
| 219 | , 1, |
| 220 | PLC6, 1, |
| 221 | PLC7, 1, |
| 222 | Offset(0x3B), /* PMEStatus1 */ |
| 223 | GP0S, 1, |
| 224 | GM4S, 1, |
| 225 | GM5S, 1, |
| 226 | APS, 1, |
| 227 | GM6S, 1, |
| 228 | GM7S, 1, |
| 229 | GP2S, 1, |
| 230 | STSS, 1, |
| 231 | Offset(0x55), /* SoftPciRst */ |
| 232 | SPRE, 1, |
| 233 | , 1, |
| 234 | , 1, |
| 235 | PNAT, 1, |
| 236 | PWMK, 1, |
| 237 | PWNS, 1, |
| 238 | |
| 239 | /* Offset(0x61), */ /* Options_1 */ |
| 240 | /* ,7, */ |
| 241 | /* R617,1, */ |
| 242 | |
| 243 | Offset(0x65), /* UsbPMControl */ |
| 244 | , 4, |
| 245 | URRE, 1, |
| 246 | Offset(0x68), /* MiscEnable68 */ |
| 247 | , 3, |
| 248 | TMTE, 1, |
| 249 | , 1, |
| 250 | Offset(0x92), /* GEVENTIN */ |
| 251 | , 7, |
| 252 | E7IS, 1, |
| 253 | Offset(0x96), /* GPM98IN */ |
| 254 | G8IS, 1, |
| 255 | G9IS, 1, |
| 256 | Offset(0x9A), /* EnhanceControl */ |
| 257 | ,7, |
| 258 | HPDE, 1, |
| 259 | Offset(0xA8), /* PIO7654Enable */ |
| 260 | IO4E, 1, |
| 261 | IO5E, 1, |
| 262 | IO6E, 1, |
| 263 | IO7E, 1, |
| 264 | Offset(0xA9), /* PIO7654Status */ |
| 265 | IO4S, 1, |
| 266 | IO5S, 1, |
| 267 | IO6S, 1, |
| 268 | IO7S, 1, |
| 269 | } |
| 270 | |
| 271 | /* PM1 Event Block |
| 272 | * First word is PM1_Status, Second word is PM1_Enable |
| 273 | */ |
| 274 | OperationRegion(P1EB, SystemIO, APEB, 0x04) |
| 275 | Field(P1EB, ByteAcc, NoLock, Preserve) { |
| 276 | TMST, 1, |
| 277 | , 3, |
| 278 | BMST, 1, |
| 279 | GBST, 1, |
| 280 | Offset(0x01), |
| 281 | PBST, 1, |
| 282 | , 1, |
| 283 | RTST, 1, |
| 284 | , 3, |
| 285 | PWST, 1, |
| 286 | SPWS, 1, |
| 287 | Offset(0x02), |
| 288 | TMEN, 1, |
| 289 | , 4, |
| 290 | GBEN, 1, |
| 291 | Offset(0x03), |
| 292 | PBEN, 1, |
| 293 | , 1, |
| 294 | RTEN, 1, |
| 295 | , 3, |
| 296 | PWDA, 1, |
| 297 | } |
| 298 | |
| 299 | Scope(\_SB) { |
| 300 | /* PCIe Configuration Space for 16 busses */ |
| 301 | OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ |
| 302 | Field(PCFG, ByteAcc, NoLock, Preserve) { |
| 303 | /* Byte offsets are computed using the following technique: |
| 304 | * ((bus number + 1) * ((device number * 8) * 4096)) + register offset |
| 305 | * The 8 comes from 8 functions per device, and 4096 bytes per function config space |
| 306 | */ |
| 307 | Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ |
| 308 | STB5, 32, |
| 309 | Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ |
| 310 | PT0D, 1, |
| 311 | PT1D, 1, |
| 312 | PT2D, 1, |
| 313 | PT3D, 1, |
| 314 | PT4D, 1, |
| 315 | PT5D, 1, |
| 316 | PT6D, 1, |
| 317 | PT7D, 1, |
| 318 | PT8D, 1, |
| 319 | PT9D, 1, |
| 320 | Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ |
| 321 | SBIE, 1, |
| 322 | SBME, 1, |
| 323 | Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ |
| 324 | SBRI, 8, |
| 325 | Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ |
| 326 | SBB1, 32, |
| 327 | Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ |
| 328 | ,14, |
| 329 | P92E, 1, /* Port92 decode enable */ |
| 330 | } |
| 331 | |
| 332 | OperationRegion(SB5, SystemMemory, STB5, 0x1000) |
| 333 | Field(SB5, AnyAcc, NoLock, Preserve){ |
| 334 | /* Port 0 */ |
| 335 | Offset(0x120), /* Port 0 Task file status */ |
| 336 | P0ER, 1, |
| 337 | , 2, |
| 338 | P0DQ, 1, |
| 339 | , 3, |
| 340 | P0BY, 1, |
| 341 | Offset(0x128), /* Port 0 Serial ATA status */ |
| 342 | P0DD, 4, |
| 343 | , 4, |
| 344 | P0IS, 4, |
| 345 | Offset(0x12C), /* Port 0 Serial ATA control */ |
| 346 | P0DI, 4, |
| 347 | Offset(0x130), /* Port 0 Serial ATA error */ |
| 348 | , 16, |
| 349 | P0PR, 1, |
| 350 | |
| 351 | /* Port 1 */ |
| 352 | offset(0x1A0), /* Port 1 Task file status */ |
| 353 | P1ER, 1, |
| 354 | , 2, |
| 355 | P1DQ, 1, |
| 356 | , 3, |
| 357 | P1BY, 1, |
| 358 | Offset(0x1A8), /* Port 1 Serial ATA status */ |
| 359 | P1DD, 4, |
| 360 | , 4, |
| 361 | P1IS, 4, |
| 362 | Offset(0x1AC), /* Port 1 Serial ATA control */ |
| 363 | P1DI, 4, |
| 364 | Offset(0x1B0), /* Port 1 Serial ATA error */ |
| 365 | , 16, |
| 366 | P1PR, 1, |
| 367 | |
| 368 | /* Port 2 */ |
| 369 | Offset(0x220), /* Port 2 Task file status */ |
| 370 | P2ER, 1, |
| 371 | , 2, |
| 372 | P2DQ, 1, |
| 373 | , 3, |
| 374 | P2BY, 1, |
| 375 | Offset(0x228), /* Port 2 Serial ATA status */ |
| 376 | P2DD, 4, |
| 377 | , 4, |
| 378 | P2IS, 4, |
| 379 | Offset(0x22C), /* Port 2 Serial ATA control */ |
| 380 | P2DI, 4, |
| 381 | Offset(0x230), /* Port 2 Serial ATA error */ |
| 382 | , 16, |
| 383 | P2PR, 1, |
| 384 | |
| 385 | /* Port 3 */ |
| 386 | Offset(0x2A0), /* Port 3 Task file status */ |
| 387 | P3ER, 1, |
| 388 | , 2, |
| 389 | P3DQ, 1, |
| 390 | , 3, |
| 391 | P3BY, 1, |
| 392 | Offset(0x2A8), /* Port 3 Serial ATA status */ |
| 393 | P3DD, 4, |
| 394 | , 4, |
| 395 | P3IS, 4, |
| 396 | Offset(0x2AC), /* Port 3 Serial ATA control */ |
| 397 | P3DI, 4, |
| 398 | Offset(0x2B0), /* Port 3 Serial ATA error */ |
| 399 | , 16, |
| 400 | P3PR, 1, |
| 401 | } |
| 402 | } |
| 403 | |
| 404 | |
| 405 | #include "acpi/routing.asl" |
| 406 | |
| 407 | Scope(\_SB) { |
| 408 | |
Edward O'Callaghan | f7d8f09 | 2014-05-31 13:57:52 +1000 | [diff] [blame] | 409 | Method(OSFL, 0){ |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 410 | |
Edward O'Callaghan | f7d8f09 | 2014-05-31 13:57:52 +1000 | [diff] [blame] | 411 | if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 412 | |
Martin Roth | 91d9cbc | 2015-12-08 15:04:23 -0700 | [diff] [blame] | 413 | if(CondRefOf(\_OSI)) |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 414 | { |
Edward O'Callaghan | f7d8f09 | 2014-05-31 13:57:52 +1000 | [diff] [blame] | 415 | Store(1, OSVR) /* Assume some form of XP */ |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 416 | if (\_OSI("Windows 2006")) /* Vista */ |
| 417 | { |
Edward O'Callaghan | f7d8f09 | 2014-05-31 13:57:52 +1000 | [diff] [blame] | 418 | Store(2, OSVR) |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 419 | } |
| 420 | } else { |
| 421 | If(WCMP(\_OS,"Linux")) { |
Edward O'Callaghan | f7d8f09 | 2014-05-31 13:57:52 +1000 | [diff] [blame] | 422 | Store(3, OSVR) /* Linux */ |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 423 | } Else { |
Edward O'Callaghan | f7d8f09 | 2014-05-31 13:57:52 +1000 | [diff] [blame] | 424 | Store(4, OSVR) /* Gotta be WinCE */ |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 425 | } |
| 426 | } |
Edward O'Callaghan | f7d8f09 | 2014-05-31 13:57:52 +1000 | [diff] [blame] | 427 | Return(OSVR) |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 428 | } |
| 429 | |
| 430 | Method(_PIC, 0x01, NotSerialized) |
| 431 | { |
| 432 | If (Arg0) |
| 433 | { |
| 434 | \_SB.CIRQ() |
| 435 | } |
| 436 | Store(Arg0, PMOD) |
| 437 | } |
| 438 | Method(CIRQ, 0x00, NotSerialized){ |
| 439 | Store(0, PIRA) |
| 440 | Store(0, PIRB) |
| 441 | Store(0, PIRC) |
| 442 | Store(0, PIRD) |
| 443 | Store(0, PIRE) |
| 444 | Store(0, PIRF) |
| 445 | Store(0, PIRG) |
| 446 | Store(0, PIRH) |
| 447 | } |
| 448 | |
| 449 | Name(IRQB, ResourceTemplate(){ |
| 450 | IRQ(Level,ActiveLow,Shared){15} |
| 451 | }) |
| 452 | |
| 453 | Name(IRQP, ResourceTemplate(){ |
| 454 | IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} |
| 455 | }) |
| 456 | |
| 457 | Name(PITF, ResourceTemplate(){ |
| 458 | IRQ(Level,ActiveLow,Exclusive){9} |
| 459 | }) |
| 460 | |
| 461 | Device(INTA) { |
| 462 | Name(_HID, EISAID("PNP0C0F")) |
| 463 | Name(_UID, 1) |
| 464 | |
| 465 | Method(_STA, 0) { |
| 466 | if (PIRA) { |
| 467 | Return(0x0B) /* sata is invisible */ |
| 468 | } else { |
| 469 | Return(0x09) /* sata is disabled */ |
| 470 | } |
| 471 | } /* End Method(_SB.INTA._STA) */ |
| 472 | |
| 473 | Method(_DIS ,0) { |
| 474 | /* DBGO("\\_SB\\LNKA\\_DIS\n") */ |
| 475 | Store(0, PIRA) |
| 476 | } /* End Method(_SB.INTA._DIS) */ |
| 477 | |
| 478 | Method(_PRS ,0) { |
| 479 | /* DBGO("\\_SB\\LNKA\\_PRS\n") */ |
| 480 | Return(IRQP) |
| 481 | } /* Method(_SB.INTA._PRS) */ |
| 482 | |
| 483 | Method(_CRS ,0) { |
| 484 | /* DBGO("\\_SB\\LNKA\\_CRS\n") */ |
| 485 | CreateWordField(IRQB, 0x1, IRQN) |
| 486 | ShiftLeft(1, PIRA, IRQN) |
| 487 | Return(IRQB) |
| 488 | } /* Method(_SB.INTA._CRS) */ |
| 489 | |
| 490 | Method(_SRS, 1) { |
| 491 | /* DBGO("\\_SB\\LNKA\\_CRS\n") */ |
| 492 | CreateWordField(ARG0, 1, IRQM) |
| 493 | |
| 494 | /* Use lowest available IRQ */ |
| 495 | FindSetRightBit(IRQM, Local0) |
| 496 | if (Local0) { |
| 497 | Decrement(Local0) |
| 498 | } |
| 499 | Store(Local0, PIRA) |
| 500 | } /* End Method(_SB.INTA._SRS) */ |
| 501 | } /* End Device(INTA) */ |
| 502 | |
| 503 | Device(INTB) { |
| 504 | Name(_HID, EISAID("PNP0C0F")) |
| 505 | Name(_UID, 2) |
| 506 | |
| 507 | Method(_STA, 0) { |
| 508 | if (PIRB) { |
| 509 | Return(0x0B) /* sata is invisible */ |
| 510 | } else { |
| 511 | Return(0x09) /* sata is disabled */ |
| 512 | } |
| 513 | } /* End Method(_SB.INTB._STA) */ |
| 514 | |
| 515 | Method(_DIS ,0) { |
| 516 | /* DBGO("\\_SB\\LNKB\\_DIS\n") */ |
| 517 | Store(0, PIRB) |
| 518 | } /* End Method(_SB.INTB._DIS) */ |
| 519 | |
| 520 | Method(_PRS ,0) { |
| 521 | /* DBGO("\\_SB\\LNKB\\_PRS\n") */ |
| 522 | Return(IRQP) |
| 523 | } /* Method(_SB.INTB._PRS) */ |
| 524 | |
| 525 | Method(_CRS ,0) { |
| 526 | /* DBGO("\\_SB\\LNKB\\_CRS\n") */ |
| 527 | CreateWordField(IRQB, 0x1, IRQN) |
| 528 | ShiftLeft(1, PIRB, IRQN) |
| 529 | Return(IRQB) |
| 530 | } /* Method(_SB.INTB._CRS) */ |
| 531 | |
| 532 | Method(_SRS, 1) { |
| 533 | /* DBGO("\\_SB\\LNKB\\_CRS\n") */ |
| 534 | CreateWordField(ARG0, 1, IRQM) |
| 535 | |
| 536 | /* Use lowest available IRQ */ |
| 537 | FindSetRightBit(IRQM, Local0) |
| 538 | if (Local0) { |
| 539 | Decrement(Local0) |
| 540 | } |
| 541 | Store(Local0, PIRB) |
| 542 | } /* End Method(_SB.INTB._SRS) */ |
| 543 | } /* End Device(INTB) */ |
| 544 | |
| 545 | Device(INTC) { |
| 546 | Name(_HID, EISAID("PNP0C0F")) |
| 547 | Name(_UID, 3) |
| 548 | |
| 549 | Method(_STA, 0) { |
| 550 | if (PIRC) { |
| 551 | Return(0x0B) /* sata is invisible */ |
| 552 | } else { |
| 553 | Return(0x09) /* sata is disabled */ |
| 554 | } |
| 555 | } /* End Method(_SB.INTC._STA) */ |
| 556 | |
| 557 | Method(_DIS ,0) { |
| 558 | /* DBGO("\\_SB\\LNKC\\_DIS\n") */ |
| 559 | Store(0, PIRC) |
| 560 | } /* End Method(_SB.INTC._DIS) */ |
| 561 | |
| 562 | Method(_PRS ,0) { |
| 563 | /* DBGO("\\_SB\\LNKC\\_PRS\n") */ |
| 564 | Return(IRQP) |
| 565 | } /* Method(_SB.INTC._PRS) */ |
| 566 | |
| 567 | Method(_CRS ,0) { |
| 568 | /* DBGO("\\_SB\\LNKC\\_CRS\n") */ |
| 569 | CreateWordField(IRQB, 0x1, IRQN) |
| 570 | ShiftLeft(1, PIRC, IRQN) |
| 571 | Return(IRQB) |
| 572 | } /* Method(_SB.INTC._CRS) */ |
| 573 | |
| 574 | Method(_SRS, 1) { |
| 575 | /* DBGO("\\_SB\\LNKC\\_CRS\n") */ |
| 576 | CreateWordField(ARG0, 1, IRQM) |
| 577 | |
| 578 | /* Use lowest available IRQ */ |
| 579 | FindSetRightBit(IRQM, Local0) |
| 580 | if (Local0) { |
| 581 | Decrement(Local0) |
| 582 | } |
| 583 | Store(Local0, PIRC) |
| 584 | } /* End Method(_SB.INTC._SRS) */ |
| 585 | } /* End Device(INTC) */ |
| 586 | |
| 587 | Device(INTD) { |
| 588 | Name(_HID, EISAID("PNP0C0F")) |
| 589 | Name(_UID, 4) |
| 590 | |
| 591 | Method(_STA, 0) { |
| 592 | if (PIRD) { |
| 593 | Return(0x0B) /* sata is invisible */ |
| 594 | } else { |
| 595 | Return(0x09) /* sata is disabled */ |
| 596 | } |
| 597 | } /* End Method(_SB.INTD._STA) */ |
| 598 | |
| 599 | Method(_DIS ,0) { |
| 600 | /* DBGO("\\_SB\\LNKD\\_DIS\n") */ |
| 601 | Store(0, PIRD) |
| 602 | } /* End Method(_SB.INTD._DIS) */ |
| 603 | |
| 604 | Method(_PRS ,0) { |
| 605 | /* DBGO("\\_SB\\LNKD\\_PRS\n") */ |
| 606 | Return(IRQP) |
| 607 | } /* Method(_SB.INTD._PRS) */ |
| 608 | |
| 609 | Method(_CRS ,0) { |
| 610 | /* DBGO("\\_SB\\LNKD\\_CRS\n") */ |
| 611 | CreateWordField(IRQB, 0x1, IRQN) |
| 612 | ShiftLeft(1, PIRD, IRQN) |
| 613 | Return(IRQB) |
| 614 | } /* Method(_SB.INTD._CRS) */ |
| 615 | |
| 616 | Method(_SRS, 1) { |
| 617 | /* DBGO("\\_SB\\LNKD\\_CRS\n") */ |
| 618 | CreateWordField(ARG0, 1, IRQM) |
| 619 | |
| 620 | /* Use lowest available IRQ */ |
| 621 | FindSetRightBit(IRQM, Local0) |
| 622 | if (Local0) { |
| 623 | Decrement(Local0) |
| 624 | } |
| 625 | Store(Local0, PIRD) |
| 626 | } /* End Method(_SB.INTD._SRS) */ |
| 627 | } /* End Device(INTD) */ |
| 628 | |
| 629 | Device(INTE) { |
| 630 | Name(_HID, EISAID("PNP0C0F")) |
| 631 | Name(_UID, 5) |
| 632 | |
| 633 | Method(_STA, 0) { |
| 634 | if (PIRE) { |
| 635 | Return(0x0B) /* sata is invisible */ |
| 636 | } else { |
| 637 | Return(0x09) /* sata is disabled */ |
| 638 | } |
| 639 | } /* End Method(_SB.INTE._STA) */ |
| 640 | |
| 641 | Method(_DIS ,0) { |
| 642 | /* DBGO("\\_SB\\LNKE\\_DIS\n") */ |
| 643 | Store(0, PIRE) |
| 644 | } /* End Method(_SB.INTE._DIS) */ |
| 645 | |
| 646 | Method(_PRS ,0) { |
| 647 | /* DBGO("\\_SB\\LNKE\\_PRS\n") */ |
| 648 | Return(IRQP) |
| 649 | } /* Method(_SB.INTE._PRS) */ |
| 650 | |
| 651 | Method(_CRS ,0) { |
| 652 | /* DBGO("\\_SB\\LNKE\\_CRS\n") */ |
| 653 | CreateWordField(IRQB, 0x1, IRQN) |
| 654 | ShiftLeft(1, PIRE, IRQN) |
| 655 | Return(IRQB) |
| 656 | } /* Method(_SB.INTE._CRS) */ |
| 657 | |
| 658 | Method(_SRS, 1) { |
| 659 | /* DBGO("\\_SB\\LNKE\\_CRS\n") */ |
| 660 | CreateWordField(ARG0, 1, IRQM) |
| 661 | |
| 662 | /* Use lowest available IRQ */ |
| 663 | FindSetRightBit(IRQM, Local0) |
| 664 | if (Local0) { |
| 665 | Decrement(Local0) |
| 666 | } |
| 667 | Store(Local0, PIRE) |
| 668 | } /* End Method(_SB.INTE._SRS) */ |
| 669 | } /* End Device(INTE) */ |
| 670 | |
| 671 | Device(INTF) { |
| 672 | Name(_HID, EISAID("PNP0C0F")) |
| 673 | Name(_UID, 6) |
| 674 | |
| 675 | Method(_STA, 0) { |
| 676 | if (PIRF) { |
| 677 | Return(0x0B) /* sata is invisible */ |
| 678 | } else { |
| 679 | Return(0x09) /* sata is disabled */ |
| 680 | } |
| 681 | } /* End Method(_SB.INTF._STA) */ |
| 682 | |
| 683 | Method(_DIS ,0) { |
| 684 | /* DBGO("\\_SB\\LNKF\\_DIS\n") */ |
| 685 | Store(0, PIRF) |
| 686 | } /* End Method(_SB.INTF._DIS) */ |
| 687 | |
| 688 | Method(_PRS ,0) { |
| 689 | /* DBGO("\\_SB\\LNKF\\_PRS\n") */ |
| 690 | Return(PITF) |
| 691 | } /* Method(_SB.INTF._PRS) */ |
| 692 | |
| 693 | Method(_CRS ,0) { |
| 694 | /* DBGO("\\_SB\\LNKF\\_CRS\n") */ |
| 695 | CreateWordField(IRQB, 0x1, IRQN) |
| 696 | ShiftLeft(1, PIRF, IRQN) |
| 697 | Return(IRQB) |
| 698 | } /* Method(_SB.INTF._CRS) */ |
| 699 | |
| 700 | Method(_SRS, 1) { |
| 701 | /* DBGO("\\_SB\\LNKF\\_CRS\n") */ |
| 702 | CreateWordField(ARG0, 1, IRQM) |
| 703 | |
| 704 | /* Use lowest available IRQ */ |
| 705 | FindSetRightBit(IRQM, Local0) |
| 706 | if (Local0) { |
| 707 | Decrement(Local0) |
| 708 | } |
| 709 | Store(Local0, PIRF) |
| 710 | } /* End Method(_SB.INTF._SRS) */ |
| 711 | } /* End Device(INTF) */ |
| 712 | |
| 713 | Device(INTG) { |
| 714 | Name(_HID, EISAID("PNP0C0F")) |
| 715 | Name(_UID, 7) |
| 716 | |
| 717 | Method(_STA, 0) { |
| 718 | if (PIRG) { |
| 719 | Return(0x0B) /* sata is invisible */ |
| 720 | } else { |
| 721 | Return(0x09) /* sata is disabled */ |
| 722 | } |
| 723 | } /* End Method(_SB.INTG._STA) */ |
| 724 | |
| 725 | Method(_DIS ,0) { |
| 726 | /* DBGO("\\_SB\\LNKG\\_DIS\n") */ |
| 727 | Store(0, PIRG) |
| 728 | } /* End Method(_SB.INTG._DIS) */ |
| 729 | |
| 730 | Method(_PRS ,0) { |
| 731 | /* DBGO("\\_SB\\LNKG\\_PRS\n") */ |
| 732 | Return(IRQP) |
| 733 | } /* Method(_SB.INTG._CRS) */ |
| 734 | |
| 735 | Method(_CRS ,0) { |
| 736 | /* DBGO("\\_SB\\LNKG\\_CRS\n") */ |
| 737 | CreateWordField(IRQB, 0x1, IRQN) |
| 738 | ShiftLeft(1, PIRG, IRQN) |
| 739 | Return(IRQB) |
| 740 | } /* Method(_SB.INTG._CRS) */ |
| 741 | |
| 742 | Method(_SRS, 1) { |
| 743 | /* DBGO("\\_SB\\LNKG\\_CRS\n") */ |
| 744 | CreateWordField(ARG0, 1, IRQM) |
| 745 | |
| 746 | /* Use lowest available IRQ */ |
| 747 | FindSetRightBit(IRQM, Local0) |
| 748 | if (Local0) { |
| 749 | Decrement(Local0) |
| 750 | } |
| 751 | Store(Local0, PIRG) |
| 752 | } /* End Method(_SB.INTG._SRS) */ |
| 753 | } /* End Device(INTG) */ |
| 754 | |
| 755 | Device(INTH) { |
| 756 | Name(_HID, EISAID("PNP0C0F")) |
| 757 | Name(_UID, 8) |
| 758 | |
| 759 | Method(_STA, 0) { |
| 760 | if (PIRH) { |
| 761 | Return(0x0B) /* sata is invisible */ |
| 762 | } else { |
| 763 | Return(0x09) /* sata is disabled */ |
| 764 | } |
| 765 | } /* End Method(_SB.INTH._STA) */ |
| 766 | |
| 767 | Method(_DIS ,0) { |
| 768 | /* DBGO("\\_SB\\LNKH\\_DIS\n") */ |
| 769 | Store(0, PIRH) |
| 770 | } /* End Method(_SB.INTH._DIS) */ |
| 771 | |
| 772 | Method(_PRS ,0) { |
| 773 | /* DBGO("\\_SB\\LNKH\\_PRS\n") */ |
| 774 | Return(IRQP) |
| 775 | } /* Method(_SB.INTH._CRS) */ |
| 776 | |
| 777 | Method(_CRS ,0) { |
| 778 | /* DBGO("\\_SB\\LNKH\\_CRS\n") */ |
| 779 | CreateWordField(IRQB, 0x1, IRQN) |
| 780 | ShiftLeft(1, PIRH, IRQN) |
| 781 | Return(IRQB) |
| 782 | } /* Method(_SB.INTH._CRS) */ |
| 783 | |
| 784 | Method(_SRS, 1) { |
| 785 | /* DBGO("\\_SB\\LNKH\\_CRS\n") */ |
| 786 | CreateWordField(ARG0, 1, IRQM) |
| 787 | |
| 788 | /* Use lowest available IRQ */ |
| 789 | FindSetRightBit(IRQM, Local0) |
| 790 | if (Local0) { |
| 791 | Decrement(Local0) |
| 792 | } |
| 793 | Store(Local0, PIRH) |
| 794 | } /* End Method(_SB.INTH._SRS) */ |
| 795 | } /* End Device(INTH) */ |
| 796 | |
| 797 | } /* End Scope(_SB) */ |
| 798 | |
| 799 | |
| 800 | /* Supported sleep states: */ |
| 801 | Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ |
| 802 | |
| 803 | If (LAnd(SSFG, 0x01)) { |
| 804 | Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ |
| 805 | } |
| 806 | If (LAnd(SSFG, 0x02)) { |
| 807 | Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ |
| 808 | } |
| 809 | If (LAnd(SSFG, 0x04)) { |
| 810 | Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ |
| 811 | } |
| 812 | If (LAnd(SSFG, 0x08)) { |
| 813 | Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ |
| 814 | } |
| 815 | |
| 816 | Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ |
| 817 | |
| 818 | Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ |
| 819 | Name(CSMS, 0) /* Current System State */ |
| 820 | |
| 821 | /* Wake status package */ |
| 822 | Name(WKST,Package(){Zero, Zero}) |
| 823 | |
| 824 | /* |
| 825 | * \_PTS - Prepare to Sleep method |
| 826 | * |
| 827 | * Entry: |
| 828 | * Arg0=The value of the sleeping state S1=1, S2=2, etc |
| 829 | * |
| 830 | * Exit: |
| 831 | * -none- |
| 832 | * |
| 833 | * The _PTS control method is executed at the beginning of the sleep process |
| 834 | * for S1-S5. The sleeping value is passed to the _PTS control method. This |
| 835 | * control method may be executed a relatively long time before entering the |
| 836 | * sleep state and the OS may abort the operation without notification to |
| 837 | * the ACPI driver. This method cannot modify the configuration or power |
| 838 | * state of any device in the system. |
| 839 | */ |
| 840 | Method(\_PTS, 1) { |
Zheng Bao | 8ae82e3 | 2011-01-20 06:28:25 +0000 | [diff] [blame] | 841 | /* DBGO("\\_PTS\n") */ |
| 842 | /* DBGO("From S0 to S") */ |
| 843 | /* DBGO(Arg0) */ |
| 844 | /* DBGO("\n") */ |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 845 | |
| 846 | /* Don't allow PCIRST# to reset USB */ |
| 847 | if (LEqual(Arg0,3)){ |
| 848 | Store(0,URRE) |
| 849 | } |
| 850 | |
| 851 | /* Clear sleep SMI status flag and enable sleep SMI trap. */ |
| 852 | /*Store(One, CSSM) |
| 853 | Store(One, SSEN)*/ |
| 854 | |
| 855 | /* On older chips, clear PciExpWakeDisEn */ |
| 856 | /*if (LLessEqual(\_SB.SBRI, 0x13)) { |
| 857 | * Store(0,\_SB.PWDE) |
| 858 | *} |
| 859 | */ |
| 860 | |
| 861 | /* Clear wake status structure. */ |
| 862 | Store(0, Index(WKST,0)) |
| 863 | Store(0, Index(WKST,1)) |
| 864 | } /* End Method(\_PTS) */ |
| 865 | |
| 866 | /* |
| 867 | * The following method results in a "not a valid reserved NameSeg" |
| 868 | * warning so I have commented it out for the duration. It isn't |
| 869 | * used, so it could be removed. |
| 870 | * |
| 871 | * |
| 872 | * \_GTS OEM Going To Sleep method |
| 873 | * |
| 874 | * Entry: |
| 875 | * Arg0=The value of the sleeping state S1=1, S2=2 |
| 876 | * |
| 877 | * Exit: |
| 878 | * -none- |
| 879 | * |
| 880 | * Method(\_GTS, 1) { |
| 881 | * DBGO("\\_GTS\n") |
| 882 | * DBGO("From S0 to S") |
| 883 | * DBGO(Arg0) |
| 884 | * DBGO("\n") |
| 885 | * } |
| 886 | */ |
| 887 | |
| 888 | /* |
| 889 | * \_BFS OEM Back From Sleep method |
| 890 | * |
| 891 | * Entry: |
| 892 | * Arg0=The value of the sleeping state S1=1, S2=2 |
| 893 | * |
| 894 | * Exit: |
| 895 | * -none- |
| 896 | */ |
| 897 | Method(\_BFS, 1) { |
| 898 | /* DBGO("\\_BFS\n") */ |
| 899 | /* DBGO("From S") */ |
| 900 | /* DBGO(Arg0) */ |
| 901 | /* DBGO(" to S0\n") */ |
| 902 | } |
| 903 | |
| 904 | /* |
| 905 | * \_WAK System Wake method |
| 906 | * |
| 907 | * Entry: |
| 908 | * Arg0=The value of the sleeping state S1=1, S2=2 |
| 909 | * |
| 910 | * Exit: |
| 911 | * Return package of 2 DWords |
| 912 | * Dword 1 - Status |
| 913 | * 0x00000000 wake succeeded |
| 914 | * 0x00000001 Wake was signaled but failed due to lack of power |
| 915 | * 0x00000002 Wake was signaled but failed due to thermal condition |
| 916 | * Dword 2 - Power Supply state |
| 917 | * if non-zero the effective S-state the power supply entered |
| 918 | */ |
| 919 | Method(\_WAK, 1) { |
Zheng Bao | 8ae82e3 | 2011-01-20 06:28:25 +0000 | [diff] [blame] | 920 | /* DBGO("\\_WAK\n") */ |
| 921 | /* DBGO("From S") */ |
| 922 | /* DBGO(Arg0) */ |
| 923 | /* DBGO(" to S0\n") */ |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 924 | |
| 925 | /* Re-enable HPET */ |
| 926 | Store(1,HPDE) |
| 927 | |
| 928 | /* Restore PCIRST# so it resets USB */ |
| 929 | if (LEqual(Arg0,3)){ |
| 930 | Store(1,URRE) |
| 931 | } |
| 932 | |
| 933 | /* Arbitrarily clear PciExpWakeStatus */ |
Martin Roth | f77516c | 2015-12-08 14:00:07 -0700 | [diff] [blame] | 934 | Store(PWST, Local1) |
| 935 | Store(Local1, PWST) |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 936 | |
| 937 | /* if(DeRefOf(Index(WKST,0))) { |
| 938 | * Store(0, Index(WKST,1)) |
| 939 | * } else { |
| 940 | * Store(Arg0, Index(WKST,1)) |
| 941 | * } |
| 942 | */ |
| 943 | Return(WKST) |
| 944 | } /* End Method(\_WAK) */ |
| 945 | |
| 946 | Scope(\_GPE) { /* Start Scope GPE */ |
| 947 | /* General event 0 */ |
| 948 | /* Method(_L00) { |
| 949 | * DBGO("\\_GPE\\_L00\n") |
| 950 | * } |
| 951 | */ |
| 952 | |
| 953 | /* General event 1 */ |
| 954 | /* Method(_L01) { |
| 955 | * DBGO("\\_GPE\\_L00\n") |
| 956 | * } |
| 957 | */ |
| 958 | |
| 959 | /* General event 2 */ |
| 960 | /* Method(_L02) { |
| 961 | * DBGO("\\_GPE\\_L00\n") |
| 962 | * } |
| 963 | */ |
| 964 | |
| 965 | /* General event 3 */ |
| 966 | Method(_L03) { |
| 967 | /* DBGO("\\_GPE\\_L00\n") */ |
| 968 | Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ |
| 969 | } |
| 970 | |
| 971 | /* General event 4 */ |
| 972 | /* Method(_L04) { |
| 973 | * DBGO("\\_GPE\\_L00\n") |
| 974 | * } |
| 975 | */ |
| 976 | |
| 977 | /* General event 5 */ |
| 978 | /* Method(_L05) { |
| 979 | * DBGO("\\_GPE\\_L00\n") |
| 980 | * } |
| 981 | */ |
| 982 | |
| 983 | /* General event 6 - Used for GPM6, moved to USB.asl */ |
| 984 | /* Method(_L06) { |
| 985 | * DBGO("\\_GPE\\_L00\n") |
| 986 | * } |
| 987 | */ |
| 988 | |
| 989 | /* General event 7 - Used for GPM7, moved to USB.asl */ |
| 990 | /* Method(_L07) { |
| 991 | * DBGO("\\_GPE\\_L07\n") |
| 992 | * } |
| 993 | */ |
| 994 | |
| 995 | /* Legacy PM event */ |
| 996 | Method(_L08) { |
| 997 | /* DBGO("\\_GPE\\_L08\n") */ |
| 998 | } |
| 999 | |
| 1000 | /* Temp warning (TWarn) event */ |
| 1001 | Method(_L09) { |
| 1002 | /* DBGO("\\_GPE\\_L09\n") */ |
| 1003 | /* Notify (\_TZ.TZ00, 0x80) */ |
| 1004 | } |
| 1005 | |
| 1006 | /* Reserved */ |
| 1007 | /* Method(_L0A) { |
| 1008 | * DBGO("\\_GPE\\_L0A\n") |
| 1009 | * } |
| 1010 | */ |
| 1011 | |
| 1012 | /* USB controller PME# */ |
| 1013 | Method(_L0B) { |
| 1014 | /* DBGO("\\_GPE\\_L0B\n") */ |
| 1015 | Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ |
| 1016 | Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ |
| 1017 | Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ |
| 1018 | Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ |
| 1019 | Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ |
| 1020 | Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ |
| 1021 | Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ |
| 1022 | Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ |
| 1023 | } |
| 1024 | |
| 1025 | /* AC97 controller PME# */ |
| 1026 | /* Method(_L0C) { |
| 1027 | * DBGO("\\_GPE\\_L0C\n") |
| 1028 | * } |
| 1029 | */ |
| 1030 | |
| 1031 | /* OtherTherm PME# */ |
| 1032 | /* Method(_L0D) { |
| 1033 | * DBGO("\\_GPE\\_L0D\n") |
| 1034 | * } |
| 1035 | */ |
| 1036 | |
| 1037 | /* GPM9 SCI event - Moved to USB.asl */ |
| 1038 | /* Method(_L0E) { |
| 1039 | * DBGO("\\_GPE\\_L0E\n") |
| 1040 | * } |
| 1041 | */ |
| 1042 | |
| 1043 | /* PCIe HotPlug event */ |
| 1044 | /* Method(_L0F) { |
| 1045 | * DBGO("\\_GPE\\_L0F\n") |
| 1046 | * } |
| 1047 | */ |
| 1048 | |
| 1049 | /* ExtEvent0 SCI event */ |
| 1050 | Method(_L10) { |
| 1051 | /* DBGO("\\_GPE\\_L10\n") */ |
| 1052 | } |
| 1053 | |
| 1054 | |
| 1055 | /* ExtEvent1 SCI event */ |
| 1056 | Method(_L11) { |
| 1057 | /* DBGO("\\_GPE\\_L11\n") */ |
| 1058 | } |
| 1059 | |
| 1060 | /* PCIe PME# event */ |
| 1061 | /* Method(_L12) { |
| 1062 | * DBGO("\\_GPE\\_L12\n") |
| 1063 | * } |
| 1064 | */ |
| 1065 | |
| 1066 | /* GPM0 SCI event - Moved to USB.asl */ |
| 1067 | /* Method(_L13) { |
| 1068 | * DBGO("\\_GPE\\_L13\n") |
| 1069 | * } |
| 1070 | */ |
| 1071 | |
| 1072 | /* GPM1 SCI event - Moved to USB.asl */ |
| 1073 | /* Method(_L14) { |
| 1074 | * DBGO("\\_GPE\\_L14\n") |
| 1075 | * } |
| 1076 | */ |
| 1077 | |
| 1078 | /* GPM2 SCI event - Moved to USB.asl */ |
| 1079 | /* Method(_L15) { |
| 1080 | * DBGO("\\_GPE\\_L15\n") |
| 1081 | * } |
| 1082 | */ |
| 1083 | |
| 1084 | /* GPM3 SCI event - Moved to USB.asl */ |
| 1085 | /* Method(_L16) { |
| 1086 | * DBGO("\\_GPE\\_L16\n") |
| 1087 | * } |
| 1088 | */ |
| 1089 | |
| 1090 | /* GPM8 SCI event - Moved to USB.asl */ |
| 1091 | /* Method(_L17) { |
| 1092 | * DBGO("\\_GPE\\_L17\n") |
| 1093 | * } |
| 1094 | */ |
| 1095 | |
| 1096 | /* GPIO0 or GEvent8 event */ |
| 1097 | Method(_L18) { |
| 1098 | /* DBGO("\\_GPE\\_L18\n") */ |
| 1099 | Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ |
| 1100 | Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ |
| 1101 | Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ |
| 1102 | Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ |
| 1103 | Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ |
| 1104 | Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ |
| 1105 | } |
| 1106 | |
| 1107 | /* GPM4 SCI event - Moved to USB.asl */ |
| 1108 | /* Method(_L19) { |
| 1109 | * DBGO("\\_GPE\\_L19\n") |
| 1110 | * } |
| 1111 | */ |
| 1112 | |
| 1113 | /* GPM5 SCI event - Moved to USB.asl */ |
| 1114 | /* Method(_L1A) { |
| 1115 | * DBGO("\\_GPE\\_L1A\n") |
| 1116 | * } |
| 1117 | */ |
| 1118 | |
| 1119 | /* Azalia SCI event */ |
| 1120 | Method(_L1B) { |
| 1121 | /* DBGO("\\_GPE\\_L1B\n") */ |
| 1122 | Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ |
| 1123 | Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ |
| 1124 | } |
| 1125 | |
| 1126 | /* GPM6 SCI event - Reassigned to _L06 */ |
| 1127 | /* Method(_L1C) { |
| 1128 | * DBGO("\\_GPE\\_L1C\n") |
| 1129 | * } |
| 1130 | */ |
| 1131 | |
| 1132 | /* GPM7 SCI event - Reassigned to _L07 */ |
| 1133 | /* Method(_L1D) { |
| 1134 | * DBGO("\\_GPE\\_L1D\n") |
| 1135 | * } |
| 1136 | */ |
| 1137 | |
| 1138 | /* GPIO2 or GPIO66 SCI event */ |
| 1139 | /* Method(_L1E) { |
| 1140 | * DBGO("\\_GPE\\_L1E\n") |
| 1141 | * } |
| 1142 | */ |
| 1143 | |
| 1144 | /* SATA SCI event - Moved to sata.asl */ |
| 1145 | /* Method(_L1F) { |
| 1146 | * DBGO("\\_GPE\\_L1F\n") |
| 1147 | * } |
| 1148 | */ |
| 1149 | |
| 1150 | } /* End Scope GPE */ |
| 1151 | |
| 1152 | #include "acpi/usb.asl" |
| 1153 | |
| 1154 | /* South Bridge */ |
| 1155 | Scope(\_SB) { /* Start \_SB scope */ |
Patrick Georgi | 91bd306 | 2012-02-16 19:16:14 +0100 | [diff] [blame] | 1156 | #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 1157 | |
| 1158 | /* _SB.PCI0 */ |
| 1159 | /* Note: Only need HID on Primary Bus */ |
| 1160 | Device(PCI0) { |
| 1161 | External (TOM1) |
| 1162 | External (TOM2) |
| 1163 | Name(_HID, EISAID("PNP0A03")) |
| 1164 | Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ |
| 1165 | Method(_BBN, 0) { /* Bus number = 0 */ |
| 1166 | Return(0) |
| 1167 | } |
| 1168 | Method(_STA, 0) { |
| 1169 | /* DBGO("\\_SB\\PCI0\\_STA\n") */ |
| 1170 | Return(0x0B) /* Status is visible */ |
| 1171 | } |
| 1172 | |
| 1173 | Method(_PRT,0) { |
| 1174 | If(PMOD){ Return(APR0) } /* APIC mode */ |
| 1175 | Return (PR0) /* PIC Mode */ |
| 1176 | } /* end _PRT */ |
| 1177 | |
| 1178 | /* Describe the Northbridge devices */ |
| 1179 | Device(AMRT) { |
| 1180 | Name(_ADR, 0x00000000) |
| 1181 | } /* end AMRT */ |
| 1182 | |
| 1183 | /* The internal GFX bridge */ |
| 1184 | Device(AGPB) { |
| 1185 | Name(_ADR, 0x00010000) |
| 1186 | Name(_PRW, Package() {0x18, 4}) |
| 1187 | Method(_PRT,0) { |
| 1188 | Return (APR1) |
| 1189 | } |
| 1190 | } /* end AGPB */ |
| 1191 | |
| 1192 | /* The external GFX bridge */ |
| 1193 | Device(PBR2) { |
| 1194 | Name(_ADR, 0x00020000) |
| 1195 | Name(_PRW, Package() {0x18, 4}) |
| 1196 | Method(_PRT,0) { |
| 1197 | If(PMOD){ Return(APS2) } /* APIC mode */ |
| 1198 | Return (PS2) /* PIC Mode */ |
| 1199 | } /* end _PRT */ |
| 1200 | } /* end PBR2 */ |
| 1201 | |
| 1202 | /* Dev3 is also an external GFX bridge, not used in Herring */ |
| 1203 | |
| 1204 | Device(PBR4) { |
| 1205 | Name(_ADR, 0x00040000) |
| 1206 | Name(_PRW, Package() {0x18, 4}) |
| 1207 | Method(_PRT,0) { |
| 1208 | If(PMOD){ Return(APS4) } /* APIC mode */ |
| 1209 | Return (PS4) /* PIC Mode */ |
| 1210 | } /* end _PRT */ |
| 1211 | } /* end PBR4 */ |
| 1212 | |
| 1213 | Device(PBR5) { |
| 1214 | Name(_ADR, 0x00050000) |
| 1215 | Name(_PRW, Package() {0x18, 4}) |
| 1216 | Method(_PRT,0) { |
| 1217 | If(PMOD){ Return(APS5) } /* APIC mode */ |
| 1218 | Return (PS5) /* PIC Mode */ |
| 1219 | } /* end _PRT */ |
| 1220 | } /* end PBR5 */ |
| 1221 | |
| 1222 | Device(PBR6) { |
| 1223 | Name(_ADR, 0x00060000) |
| 1224 | Name(_PRW, Package() {0x18, 4}) |
| 1225 | Method(_PRT,0) { |
| 1226 | If(PMOD){ Return(APS6) } /* APIC mode */ |
| 1227 | Return (PS6) /* PIC Mode */ |
| 1228 | } /* end _PRT */ |
| 1229 | } /* end PBR6 */ |
| 1230 | |
| 1231 | /* The onboard EtherNet chip */ |
| 1232 | Device(PBR7) { |
| 1233 | Name(_ADR, 0x00070000) |
| 1234 | Name(_PRW, Package() {0x18, 4}) |
| 1235 | Method(_PRT,0) { |
| 1236 | If(PMOD){ Return(APS7) } /* APIC mode */ |
| 1237 | Return (PS7) /* PIC Mode */ |
| 1238 | } /* end _PRT */ |
| 1239 | } /* end PBR7 */ |
| 1240 | |
| 1241 | /* GPP */ |
| 1242 | Device(PBR9) { |
| 1243 | Name(_ADR, 0x00090000) |
| 1244 | Name(_PRW, Package() {0x18, 4}) |
| 1245 | Method(_PRT,0) { |
| 1246 | If(PMOD){ Return(APS9) } /* APIC mode */ |
| 1247 | Return (PS9) /* PIC Mode */ |
| 1248 | } /* end _PRT */ |
| 1249 | } /* end PBR9 */ |
| 1250 | |
| 1251 | Device(PBRa) { |
| 1252 | Name(_ADR, 0x000A0000) |
| 1253 | Name(_PRW, Package() {0x18, 4}) |
| 1254 | Method(_PRT,0) { |
| 1255 | If(PMOD){ Return(APSa) } /* APIC mode */ |
| 1256 | Return (PSa) /* PIC Mode */ |
| 1257 | } /* end _PRT */ |
| 1258 | } /* end PBRa */ |
| 1259 | |
| 1260 | Device(PE20) { |
| 1261 | Name(_ADR, 0x00150000) |
| 1262 | Name(_PRW, Package() {0x18, 4}) |
| 1263 | Method(_PRT,0) { |
| 1264 | If(PMOD){ Return(APE0) } /* APIC mode */ |
| 1265 | Return (PE0) /* PIC Mode */ |
| 1266 | } /* end _PRT */ |
| 1267 | } /* end PE20 */ |
| 1268 | Device(PE21) { |
| 1269 | Name(_ADR, 0x00150001) |
| 1270 | Name(_PRW, Package() {0x18, 4}) |
| 1271 | Method(_PRT,0) { |
| 1272 | If(PMOD){ Return(APE1) } /* APIC mode */ |
| 1273 | Return (PE1) /* PIC Mode */ |
| 1274 | } /* end _PRT */ |
| 1275 | } /* end PE21 */ |
| 1276 | Device(PE22) { |
| 1277 | Name(_ADR, 0x00150002) |
| 1278 | Name(_PRW, Package() {0x18, 4}) |
| 1279 | Method(_PRT,0) { |
| 1280 | If(PMOD){ Return(APE2) } /* APIC mode */ |
| 1281 | Return (APE2) /* PIC Mode */ |
| 1282 | } /* end _PRT */ |
| 1283 | } /* end PE22 */ |
| 1284 | Device(PE23) { |
| 1285 | Name(_ADR, 0x00150003) |
| 1286 | Name(_PRW, Package() {0x18, 4}) |
| 1287 | Method(_PRT,0) { |
| 1288 | If(PMOD){ Return(APE3) } /* APIC mode */ |
| 1289 | Return (PE3) /* PIC Mode */ |
| 1290 | } /* end _PRT */ |
| 1291 | } /* end PE23 */ |
| 1292 | |
| 1293 | /* PCI slot 1, 2, 3 */ |
| 1294 | Device(PIBR) { |
| 1295 | Name(_ADR, 0x00140004) |
| 1296 | Name(_PRW, Package() {0x18, 4}) |
| 1297 | |
| 1298 | Method(_PRT, 0) { |
| 1299 | Return (PCIB) |
| 1300 | } |
| 1301 | } |
| 1302 | |
| 1303 | /* Describe the Southbridge devices */ |
| 1304 | Device(STCR) { |
| 1305 | Name(_ADR, 0x00110000) |
| 1306 | #include "acpi/sata.asl" |
| 1307 | } /* end STCR */ |
| 1308 | |
| 1309 | Device(UOH1) { |
| 1310 | Name(_ADR, 0x00120000) |
| 1311 | Name(_PRW, Package() {0x0B, 3}) |
| 1312 | } /* end UOH1 */ |
| 1313 | |
| 1314 | Device(UOH2) { |
| 1315 | Name(_ADR, 0x00120002) |
| 1316 | Name(_PRW, Package() {0x0B, 3}) |
| 1317 | } /* end UOH2 */ |
| 1318 | |
| 1319 | Device(UOH3) { |
| 1320 | Name(_ADR, 0x00130000) |
| 1321 | Name(_PRW, Package() {0x0B, 3}) |
| 1322 | } /* end UOH3 */ |
| 1323 | |
| 1324 | Device(UOH4) { |
| 1325 | Name(_ADR, 0x00130002) |
| 1326 | Name(_PRW, Package() {0x0B, 3}) |
| 1327 | } /* end UOH4 */ |
| 1328 | |
| 1329 | Device(UOH5) { |
| 1330 | Name(_ADR, 0x00160000) |
| 1331 | Name(_PRW, Package() {0x0B, 3}) |
| 1332 | } /* end UOH5 */ |
| 1333 | |
| 1334 | Device(UOH6) { |
| 1335 | Name(_ADR, 0x00160002) |
| 1336 | Name(_PRW, Package() {0x0B, 3}) |
| 1337 | } /* end UOH5 */ |
| 1338 | |
| 1339 | Device(UEH1) { |
| 1340 | Name(_ADR, 0x00140005) |
| 1341 | Name(_PRW, Package() {0x0B, 3}) |
| 1342 | } /* end UEH1 */ |
| 1343 | |
| 1344 | Device(SBUS) { |
| 1345 | Name(_ADR, 0x00140000) |
| 1346 | } /* end SBUS */ |
| 1347 | |
| 1348 | /* Primary (and only) IDE channel */ |
| 1349 | Device(IDEC) { |
| 1350 | Name(_ADR, 0x00140001) |
| 1351 | #include "acpi/ide.asl" |
| 1352 | } /* end IDEC */ |
| 1353 | |
| 1354 | Device(AZHD) { |
| 1355 | Name(_ADR, 0x00140002) |
| 1356 | OperationRegion(AZPD, PCI_Config, 0x00, 0x100) |
| 1357 | Field(AZPD, AnyAcc, NoLock, Preserve) { |
| 1358 | offset (0x42), |
| 1359 | NSDI, 1, |
| 1360 | NSDO, 1, |
| 1361 | NSEN, 1, |
| 1362 | offset (0x44), |
| 1363 | IPCR, 4, |
| 1364 | offset (0x54), |
| 1365 | PWST, 2, |
| 1366 | , 6, |
| 1367 | PMEB, 1, |
| 1368 | , 6, |
| 1369 | PMST, 1, |
| 1370 | offset (0x62), |
| 1371 | MMCR, 1, |
| 1372 | offset (0x64), |
| 1373 | MMLA, 32, |
| 1374 | offset (0x68), |
| 1375 | MMHA, 32, |
| 1376 | offset (0x6C), |
| 1377 | MMDT, 16, |
| 1378 | } |
| 1379 | |
| 1380 | Method(_INI) { |
Edward O'Callaghan | f7d8f09 | 2014-05-31 13:57:52 +1000 | [diff] [blame] | 1381 | If(LEqual(OSVR,3)){ /* If we are running Linux */ |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 1382 | Store(zero, NSEN) |
| 1383 | Store(one, NSDO) |
| 1384 | Store(one, NSDI) |
| 1385 | } |
| 1386 | } |
| 1387 | } /* end AZHD */ |
| 1388 | |
| 1389 | Device(LIBR) { |
| 1390 | Name(_ADR, 0x00140003) |
| 1391 | /* Method(_INI) { |
| 1392 | * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") |
| 1393 | } */ /* End Method(_SB.SBRDG._INI) */ |
| 1394 | |
| 1395 | /* Real Time Clock Device */ |
| 1396 | Device(RTC0) { |
| 1397 | Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ |
| 1398 | Name(_CRS, ResourceTemplate() { |
| 1399 | IRQNoFlags(){8} |
| 1400 | IO(Decode16,0x0070, 0x0070, 0, 2) |
| 1401 | /* IO(Decode16,0x0070, 0x0070, 0, 4) */ |
| 1402 | }) |
| 1403 | } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ |
| 1404 | |
| 1405 | Device(TMR) { /* Timer */ |
| 1406 | Name(_HID,EISAID("PNP0100")) /* System Timer */ |
| 1407 | Name(_CRS, ResourceTemplate() { |
| 1408 | IRQNoFlags(){0} |
| 1409 | IO(Decode16, 0x0040, 0x0040, 0, 4) |
| 1410 | /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ |
| 1411 | }) |
| 1412 | } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ |
| 1413 | |
| 1414 | Device(SPKR) { /* Speaker */ |
| 1415 | Name(_HID,EISAID("PNP0800")) /* AT style speaker */ |
| 1416 | Name(_CRS, ResourceTemplate() { |
| 1417 | IO(Decode16, 0x0061, 0x0061, 0, 1) |
| 1418 | }) |
| 1419 | } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ |
| 1420 | |
| 1421 | Device(PIC) { |
| 1422 | Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ |
| 1423 | Name(_CRS, ResourceTemplate() { |
| 1424 | IRQNoFlags(){2} |
| 1425 | IO(Decode16,0x0020, 0x0020, 0, 2) |
| 1426 | IO(Decode16,0x00A0, 0x00A0, 0, 2) |
| 1427 | /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ |
| 1428 | /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ |
| 1429 | }) |
| 1430 | } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ |
| 1431 | |
| 1432 | Device(MAD) { /* 8257 DMA */ |
| 1433 | Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ |
| 1434 | Name(_CRS, ResourceTemplate() { |
| 1435 | DMA(Compatibility,BusMaster,Transfer8){4} |
| 1436 | IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) |
| 1437 | IO(Decode16, 0x0081, 0x0081, 0x00, 0x03) |
| 1438 | IO(Decode16, 0x0087, 0x0087, 0x00, 0x01) |
| 1439 | IO(Decode16, 0x0089, 0x0089, 0x00, 0x03) |
| 1440 | IO(Decode16, 0x008F, 0x008F, 0x00, 0x01) |
| 1441 | IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) |
| 1442 | }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ |
| 1443 | } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ |
| 1444 | |
| 1445 | Device(COPR) { |
| 1446 | Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ |
| 1447 | Name(_CRS, ResourceTemplate() { |
| 1448 | IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) |
| 1449 | IRQNoFlags(){13} |
| 1450 | }) |
| 1451 | } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ |
| 1452 | #if 0 |
| 1453 | Device(HPTM) { |
| 1454 | Name(_HID,EISAID("PNP0103")) |
| 1455 | Name(CRS,ResourceTemplate() { |
| 1456 | Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ |
| 1457 | }) |
| 1458 | Method(_STA, 0) { |
| 1459 | Return(0x0F) /* sata is visible */ |
| 1460 | } |
| 1461 | Method(_CRS, 0) { |
| 1462 | CreateDwordField(CRS, ^HPT._BAS, HPBA) |
| 1463 | Store(HPBA, HPBA) |
| 1464 | Return(CRS) |
| 1465 | } |
| 1466 | } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ |
| 1467 | #endif |
| 1468 | } /* end LIBR */ |
| 1469 | |
| 1470 | Device(HPBR) { |
| 1471 | Name(_ADR, 0x00140004) |
| 1472 | } /* end HostPciBr */ |
| 1473 | |
| 1474 | Device(ACAD) { |
| 1475 | Name(_ADR, 0x00140005) |
| 1476 | } /* end Ac97audio */ |
| 1477 | |
| 1478 | Device(ACMD) { |
| 1479 | Name(_ADR, 0x00140006) |
| 1480 | } /* end Ac97modem */ |
| 1481 | |
| 1482 | Name(CRES, ResourceTemplate() { |
| 1483 | IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) |
| 1484 | |
| 1485 | WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 1486 | 0x0000, /* address granularity */ |
| 1487 | 0x0000, /* range minimum */ |
| 1488 | 0x0CF7, /* range maximum */ |
| 1489 | 0x0000, /* translation */ |
| 1490 | 0x0CF8 /* length */ |
| 1491 | ) |
| 1492 | |
| 1493 | WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 1494 | 0x0000, /* address granularity */ |
| 1495 | 0x0D00, /* range minimum */ |
| 1496 | 0xFFFF, /* range maximum */ |
| 1497 | 0x0000, /* translation */ |
| 1498 | 0xF300 /* length */ |
| 1499 | ) |
| 1500 | #if 0 |
| 1501 | Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) |
| 1502 | Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ |
| 1503 | Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ |
| 1504 | Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ |
| 1505 | |
| 1506 | /* DRAM Memory from 1MB to TopMem */ |
| 1507 | Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ |
| 1508 | |
| 1509 | /* BIOS space just below 4GB */ |
| 1510 | DWORDMemory( |
| 1511 | ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, |
| 1512 | 0x00, /* Granularity */ |
| 1513 | 0x00000000, /* Min */ |
| 1514 | 0x00000000, /* Max */ |
| 1515 | 0x00000000, /* Translation */ |
| 1516 | 0x00000000, /* Max-Min, RLEN */ |
| 1517 | ,, |
| 1518 | PCBM |
| 1519 | ) |
| 1520 | |
| 1521 | /* DRAM memory from 4GB to TopMem2 */ |
| 1522 | QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, |
| 1523 | 0xFFFFFFFF, /* Granularity */ |
| 1524 | 0x00000000, /* Min */ |
| 1525 | 0x00000000, /* Max */ |
| 1526 | 0x00000000, /* Translation */ |
| 1527 | 0x00000000, /* Max-Min, RLEN */ |
| 1528 | ,, |
| 1529 | DMHI |
| 1530 | ) |
| 1531 | |
| 1532 | /* BIOS space just below 16EB */ |
| 1533 | QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, |
| 1534 | 0xFFFFFFFF, /* Granularity */ |
| 1535 | 0x00000000, /* Min */ |
| 1536 | 0x00000000, /* Max */ |
| 1537 | 0x00000000, /* Translation */ |
| 1538 | 0x00000000, /* Max-Min, RLEN */ |
| 1539 | ,, |
| 1540 | PEBM |
| 1541 | ) |
| 1542 | #endif |
| 1543 | /* memory space for PCI BARs below 4GB */ |
| 1544 | Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) |
| 1545 | }) /* End Name(_SB.PCI0.CRES) */ |
| 1546 | |
| 1547 | Method(_CRS, 0) { |
| 1548 | /* DBGO("\\_SB\\PCI0\\_CRS\n") */ |
| 1549 | #if 0 |
| 1550 | CreateDWordField(CRES, ^EMM1._BAS, EM1B) |
| 1551 | CreateDWordField(CRES, ^EMM1._LEN, EM1L) |
| 1552 | CreateDWordField(CRES, ^DMLO._BAS, DMLB) |
| 1553 | CreateDWordField(CRES, ^DMLO._LEN, DMLL) |
| 1554 | CreateDWordField(CRES, ^PCBM._MIN, PBMB) |
| 1555 | CreateDWordField(CRES, ^PCBM._LEN, PBML) |
| 1556 | |
| 1557 | CreateQWordField(CRES, ^DMHI._MIN, DMHB) |
| 1558 | CreateQWordField(CRES, ^DMHI._LEN, DMHL) |
| 1559 | CreateQWordField(CRES, ^PEBM._MIN, EBMB) |
| 1560 | CreateQWordField(CRES, ^PEBM._LEN, EBML) |
| 1561 | |
| 1562 | If(LGreater(LOMH, 0xC0000)){ |
| 1563 | Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ |
| 1564 | Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ |
| 1565 | } |
| 1566 | |
| 1567 | /* Set size of memory from 1MB to TopMem */ |
| 1568 | Subtract(TOM1, 0x100000, DMLL) |
| 1569 | |
| 1570 | /* |
| 1571 | * If(LNotEqual(TOM2, 0x00000000)){ |
| 1572 | * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 |
| 1573 | * Subtract(TOM2, 0x100000000, DMHL) |
| 1574 | * } |
| 1575 | */ |
| 1576 | |
| 1577 | /* If there is no memory above 4GB, put the BIOS just below 4GB */ |
| 1578 | If(LEqual(TOM2, 0x00000000)){ |
| 1579 | Store(PBAD,PBMB) /* Reserve the "BIOS" space */ |
| 1580 | Store(PBLN,PBML) |
| 1581 | } |
| 1582 | Else { /* Otherwise, put the BIOS just below 16EB */ |
| 1583 | ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ |
| 1584 | Store(PBLN,EBML) |
| 1585 | } |
| 1586 | #endif |
| 1587 | CreateDWordField(CRES, ^MMIO._BAS, MM1B) |
| 1588 | CreateDWordField(CRES, ^MMIO._LEN, MM1L) |
| 1589 | /* |
| 1590 | * Declare memory between TOM1 and 4GB as available |
| 1591 | * for PCI MMIO. |
| 1592 | * Use ShiftLeft to avoid 64bit constant (for XP). |
| 1593 | * This will work even if the OS does 32bit arithmetic, as |
| 1594 | * 32bit (0x00000000 - TOM1) will wrap and give the same |
| 1595 | * result as 64bit (0x100000000 - TOM1). |
| 1596 | */ |
| 1597 | Store(TOM1, MM1B) |
| 1598 | ShiftLeft(0x10000000, 4, Local0) |
| 1599 | Subtract(Local0, TOM1, Local0) |
| 1600 | Store(Local0, MM1L) |
| 1601 | |
| 1602 | Return(CRES) /* note to change the Name buffer */ |
| 1603 | } /* end of Method(_SB.PCI0._CRS) */ |
| 1604 | |
| 1605 | /* |
| 1606 | * |
| 1607 | * FIRST METHOD CALLED UPON BOOT |
| 1608 | * |
| 1609 | * 1. If debugging, print current OS and ACPI interpreter. |
| 1610 | * 2. Get PCI Interrupt routing from ACPI VSM, this |
| 1611 | * value is based on user choice in BIOS setup. |
| 1612 | */ |
| 1613 | Method(_INI, 0) { |
| 1614 | /* DBGO("\\_SB\\_INI\n") */ |
| 1615 | /* DBGO(" DSDT.ASL code from ") */ |
| 1616 | /* DBGO(__DATE__) */ |
| 1617 | /* DBGO(" ") */ |
| 1618 | /* DBGO(__TIME__) */ |
| 1619 | /* DBGO("\n Sleep states supported: ") */ |
| 1620 | /* DBGO("\n") */ |
| 1621 | /* DBGO(" \\_OS=") */ |
| 1622 | /* DBGO(\_OS) */ |
| 1623 | /* DBGO("\n \\_REV=") */ |
| 1624 | /* DBGO(\_REV) */ |
| 1625 | /* DBGO("\n") */ |
| 1626 | |
| 1627 | /* Determine the OS we're running on */ |
Edward O'Callaghan | f7d8f09 | 2014-05-31 13:57:52 +1000 | [diff] [blame] | 1628 | OSFL() |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 1629 | |
| 1630 | /* On older chips, clear PciExpWakeDisEn */ |
| 1631 | /*if (LLessEqual(\SBRI, 0x13)) { |
| 1632 | * Store(0,\PWDE) |
| 1633 | * } |
| 1634 | */ |
| 1635 | } /* End Method(_SB._INI) */ |
| 1636 | } /* End Device(PCI0) */ |
| 1637 | |
| 1638 | Device(PWRB) { /* Start Power button device */ |
| 1639 | Name(_HID, EISAID("PNP0C0C")) |
| 1640 | Name(_UID, 0xAA) |
| 1641 | Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ |
| 1642 | Name(_STA, 0x0B) /* sata is invisible */ |
| 1643 | } |
| 1644 | } /* End \_SB scope */ |
| 1645 | |
| 1646 | Scope(\_SI) { |
| 1647 | Method(_SST, 1) { |
| 1648 | /* DBGO("\\_SI\\_SST\n") */ |
| 1649 | /* DBGO(" New Indicator state: ") */ |
| 1650 | /* DBGO(Arg0) */ |
| 1651 | /* DBGO("\n") */ |
| 1652 | } |
| 1653 | } /* End Scope SI */ |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 1654 | } |
| 1655 | /* End of ASL file */ |