WANG Siyuan | 01e3e06 | 2015-05-20 14:47:58 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
WANG Siyuan | 01e3e06 | 2015-05-20 14:47:58 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <device/device.h> |
| 18 | #include <arch/acpi.h> |
| 19 | #include <agesawrapper.h> |
WANG Siyuan | 839d68f | 2015-08-18 06:22:22 +0800 | [diff] [blame] | 20 | #include <southbridge/amd/common/amd_pci_util.h> |
| 21 | |
| 22 | /*********************************************************** |
| 23 | * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. |
| 24 | * This table is responsible for physically routing the PIC and |
| 25 | * IOAPIC IRQs to the different PCI devices on the system. It |
| 26 | * is read and written via registers 0xC00/0xC01 as an |
| 27 | * Index/Data pair. These values are chipset and mainboard |
| 28 | * dependent and should be updated accordingly. |
| 29 | * |
| 30 | * These values are used by the PCI configuration space, |
| 31 | * MP Tables. TODO: Make ACPI use these values too. |
| 32 | */ |
| 33 | const u8 mainboard_picr_data[] = { |
| 34 | [0x00] = 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F, |
| 35 | [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, |
| 36 | [0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F, |
| 37 | [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 38 | [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, |
| 39 | [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 40 | [0x30] = 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05, |
| 41 | [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 42 | [0x40] = 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00, |
| 43 | [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 44 | [0x50] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F, |
| 45 | [0x58] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, |
| 46 | [0x60] = 0x1F,0x1F,0x07,0x1F,0x1F,0x1F,0x1F,0x1F, |
| 47 | [0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, |
| 48 | [0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F, |
| 49 | [0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, |
| 50 | }; |
| 51 | |
| 52 | const u8 mainboard_intr_data[] = { |
| 53 | [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, |
| 54 | [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, |
| 55 | [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10, |
| 56 | [0x18] = 0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00, |
| 57 | [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, |
| 58 | [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 59 | [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00, |
| 60 | [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 61 | [0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00, |
| 62 | [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 63 | [0x50] = 0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00, |
| 64 | [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 65 | [0x60] = 0x1F,0x1F,0x07,0x00,0x00,0x00,0x00,0x00, |
| 66 | [0x68] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 67 | [0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F, |
| 68 | [0x78] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 69 | }; |
| 70 | |
| 71 | /* PIRQ Setup */ |
| 72 | static void pirq_setup(void) |
| 73 | { |
| 74 | intr_data_ptr = mainboard_intr_data; |
| 75 | picr_data_ptr = mainboard_picr_data; |
| 76 | } |
| 77 | |
| 78 | |
WANG Siyuan | 01e3e06 | 2015-05-20 14:47:58 +0800 | [diff] [blame] | 79 | |
| 80 | /************************************************* |
| 81 | * enable the dedicated function in bettong board. |
| 82 | *************************************************/ |
| 83 | static void bettong_enable(device_t dev) |
| 84 | { |
| 85 | printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); |
| 86 | |
| 87 | if (acpi_is_wakeup_s3()) |
| 88 | agesawrapper_fchs3earlyrestore(); |
WANG Siyuan | 839d68f | 2015-08-18 06:22:22 +0800 | [diff] [blame] | 89 | |
| 90 | /* Initialize the PIRQ data structures for consumption */ |
| 91 | pirq_setup(); |
WANG Siyuan | 01e3e06 | 2015-05-20 14:47:58 +0800 | [diff] [blame] | 92 | } |
| 93 | |
| 94 | struct chip_operations mainboard_ops = { |
| 95 | .enable_dev = bettong_enable, |
| 96 | }; |