WANG Siyuan | 01e3e06 | 2015-05-20 14:47:58 +0800 | [diff] [blame] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
| 4 | # Copyright (C) 2015 Advanced Micro Devices, Inc. |
| 5 | # |
| 6 | # This program is free software; you can redistribute it and/or modify |
| 7 | # it under the terms of the GNU General Public License as published by |
| 8 | # the Free Software Foundation; version 2 of the License. |
| 9 | # |
| 10 | # This program is distributed in the hope that it will be useful, |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | # GNU General Public License for more details. |
| 14 | # |
WANG Siyuan | 01e3e06 | 2015-05-20 14:47:58 +0800 | [diff] [blame] | 15 | chip northbridge/amd/pi/00660F01/root_complex |
| 16 | device cpu_cluster 0 on |
| 17 | chip cpu/amd/pi/00660F01 |
| 18 | device lapic 10 on end |
| 19 | end |
| 20 | end |
| 21 | |
| 22 | device domain 0 on |
| 23 | subsystemid 0x1022 0x1410 inherit |
| 24 | chip northbridge/amd/pi/00660F01 # CPU side of HT root complex |
| 25 | |
| 26 | chip northbridge/amd/pi/00660F01 # PCI side of HT root complex |
| 27 | device pci 0.0 on end # Root Complex |
| 28 | device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 |
| 29 | device pci 1.1 on end # Internal Multimedia |
| 30 | device pci 2.0 on end # PCIe Host Bridge |
| 31 | device pci 2.1 on end # x4 PCIe slot |
| 32 | device pci 2.2 on end # mPCIe slot |
| 33 | device pci 2.3 on end # Realtek NIC |
| 34 | device pci 2.4 on end # Edge Connector |
| 35 | device pci 2.5 on end # Edge Connector |
zbao | 4a2fc3e | 2015-08-16 22:45:59 -0400 | [diff] [blame] | 36 | device pci 3.0 on end # Edge Connector |
| 37 | device pci 3.1 on end # Edge Connector |
WANG Siyuan | 01e3e06 | 2015-05-20 14:47:58 +0800 | [diff] [blame] | 38 | end #chip northbridge/amd/pi/00660F01 |
| 39 | |
| 40 | chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus |
| 41 | device pci 9.0 on end # HDA |
| 42 | device pci 9.2 on end # HDA |
zbao | b0c6817 | 2015-08-26 22:29:07 -0400 | [diff] [blame] | 43 | device pci 10.0 on end # USB |
WANG Siyuan | 01e3e06 | 2015-05-20 14:47:58 +0800 | [diff] [blame] | 44 | device pci 11.0 on end # SATA |
| 45 | device pci 12.0 on end # USB |
WANG Siyuan | 01e3e06 | 2015-05-20 14:47:58 +0800 | [diff] [blame] | 46 | device pci 14.0 on # SM |
| 47 | chip drivers/generic/generic #dimm 0-0-0 |
| 48 | device i2c 50 on end |
| 49 | end |
| 50 | chip drivers/generic/generic #dimm 0-0-1 |
| 51 | device i2c 51 on end |
| 52 | end |
| 53 | end # SM |
| 54 | #device pci 14.2 on end # HDA 0x4383 |
| 55 | device pci 14.3 on end # LPC 0x439d |
| 56 | device pci 14.7 on end # SD |
| 57 | end #chip southbridge/amd/hudson |
| 58 | |
| 59 | device pci 18.0 on end |
| 60 | device pci 18.1 on end |
| 61 | device pci 18.2 on end |
| 62 | device pci 18.3 on end |
| 63 | device pci 18.4 on end |
| 64 | device pci 18.5 on end |
| 65 | register "spdAddrLookup" = " |
| 66 | { |
| 67 | { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses |
| 68 | { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses |
| 69 | }" |
| 70 | |
| 71 | end #chip northbridge/amd/pi/00660F01 # CPU side of HT root complex |
| 72 | end #domain |
| 73 | end #northbridge/amd/pi/00660F01/root_complex |