Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 Advanced Micro Devices, Inc. |
Stefan Reinauer | aeba92a | 2009-04-17 08:37:18 +0000 | [diff] [blame] | 5 | * Copyright (C) 2007-2009 coresystems GmbH |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | /* SPDs for DDR2 SDRAM */ |
| 18 | #define SPD_MEM_TYPE 2 |
| 19 | #define SPD_MEM_TYPE_SDRAM_DDR 0x07 |
| 20 | #define SPD_MEM_TYPE_SDRAM_DDR2 0x08 |
| 21 | |
| 22 | #define SPD_DIMM_TYPE 20 /* x bit0 or bit4 =1 mean registered*/ |
| 23 | #define SPD_DIMM_TYPE_RDIMM (1<<0) |
| 24 | #define SPD_DIMM_TYPE_UDIMM (1<<1) |
| 25 | #define SPD_DIMM_TYPE_SODIMM (1<<2) |
| 26 | #define SPD_DIMM_TYPE_uDIMM (1<<3) |
| 27 | #define SPD_DIMM_TYPE_mRDIMM (1<<4) |
| 28 | #define SPD_DIMM_TYPE_mUDIMM (1<<5) |
Stefan Reinauer | aeba92a | 2009-04-17 08:37:18 +0000 | [diff] [blame] | 29 | |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 30 | #define SPD_MOD_ATTRIB 21 |
| 31 | #define SPD_MOD_ATTRIB_DIFCK 0x20 |
| 32 | #define SPD_MOD_ATTRIB_REGADC 0x11 /* x */ |
| 33 | #define SPD_MOD_ATTRIB_PROBE 0x40 |
| 34 | |
| 35 | #define SPD_DEV_ATTRIB 22 /* Device attributes --- general */ |
| 36 | #define SPD_DIMM_CONF_TYPE 11 |
| 37 | #define SPD_DIMM_CONF_TYPE_ECC 0x02 |
| 38 | #define SPD_DIMM_CONF_TYPE_ADDR_PARITY 0x04 /* ? */ |
| 39 | |
Stefan Reinauer | aeba92a | 2009-04-17 08:37:18 +0000 | [diff] [blame] | 40 | #define SPD_CAS_LAT_MIN_X_1 23 |
| 41 | #define SPD_CAS_LAT_MAX_X_1 24 |
| 42 | #define SPD_CAS_LAT_MIN_X_2 25 |
| 43 | #define SPD_CAS_LAT_MAX_X_2 26 |
| 44 | |
| 45 | #define SPD_BURST_LENGTHS 16 |
| 46 | #define SPD_BURST_LENGTHS_4 (1<<2) |
| 47 | #define SPD_BURST_LENGTHS_8 (1<<3) |
| 48 | |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 49 | #define SPD_ROW_NUM 3 /* Number of Row addresses */ |
| 50 | #define SPD_COL_NUM 4 /* Number of Column addresses */ |
| 51 | #define SPD_BANK_NUM 17 /* SDRAM Device attributes - Number of Banks on |
| 52 | SDRAM device, it could be 0x4, 0x8, so address |
| 53 | lines for that would be 2, and 3 */ |
| 54 | |
| 55 | /* Number of Ranks bit [2:0], Package (bit4, 1=stack, 0=planr), Height bit[7:5] */ |
| 56 | #define SPD_MOD_ATTRIB_RANK 5 |
| 57 | #define SPD_MOD_ATTRIB_RANK_NUM_SHIFT 0 |
| 58 | #define SPD_MOD_ATTRIB_RANK_NUM_MASK 0x07 |
| 59 | #define SPD_MOD_ATTRIB_RANK_NUM_BASE 1 |
| 60 | #define SPD_MOD_ATTRIB_RANK_NUM_MIN 1 |
| 61 | #define SPD_MOD_ATTRIB_RANK_NUM_MAX 8 |
| 62 | |
| 63 | #define SPD_RANK_SIZE 31 /* Only one bit is set */ |
| 64 | #define SPD_RANK_SIZE_1GB (1<<0) |
| 65 | #define SPD_RANK_SIZE_2GB (1<<1) |
| 66 | #define SPD_RANK_SIZE_4GB (1<<2) |
| 67 | #define SPD_RANK_SIZE_8GB (1<<3) |
| 68 | #define SPD_RANK_SIZE_16GB (1<<4) |
| 69 | #define SPD_RANK_SIZE_128MB (1<<5) |
| 70 | #define SPD_RANK_SIZE_256MB (1<<6) |
| 71 | #define SPD_RANK_SIZE_512MB (1<<7) |
| 72 | |
| 73 | #define SPD_DATA_WIDTH 6 /* valid value 0, 32, 33, 36, 64, 72, 80, 128, 144, 254, 255 */ |
| 74 | #define SPD_PRI_WIDTH 13 /* Primary SDRAM Width, it could be 0x08 or 0x10 */ |
| 75 | #define SPD_ERR_WIDTH 14 /* Error Checking SDRAM Width, it could be 0x08 or 0x10 */ |
| 76 | |
| 77 | #define SPD_CAS_LAT 18 /* SDRAM Device Attributes -- CAS Latency */ |
| 78 | #define SPD_CAS_LAT_2 (1<<2) |
| 79 | #define SPD_CAS_LAT_3 (1<<3) |
| 80 | #define SPD_CAS_LAT_4 (1<<4) |
| 81 | #define SPD_CAS_LAT_5 (1<<5) |
| 82 | #define SPD_CAS_LAT_6 (1<<6) |
| 83 | |
| 84 | #define SPD_TRP 27 /* bit [7:2] = 1-63 ns, bit [1:0] 0.25ns+, final value ((val>>2) + (val & 3) * 0.25)ns */ |
| 85 | #define SPD_TRRD 28 |
| 86 | #define SPD_TRCD 29 |
| 87 | #define SPD_TRAS 30 |
| 88 | #define SPD_TWR 36 /* x */ |
| 89 | #define SPD_TWTR 37 /* x */ |
| 90 | #define SPD_TRTP 38 /* x */ |
| 91 | |
Stefan Reinauer | aeba92a | 2009-04-17 08:37:18 +0000 | [diff] [blame] | 92 | #define SPD_EX_TRC_TRFC 40 |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 93 | #define SPD_TRC 41 /* add byte 0x40 bit [3:1] , so final val41+ table[((val40>>1) & 0x7)] ... table[]={0, 0.25, 0.33, 0.5, 0.75, 0, 0}*/ |
| 94 | #define SPD_TRFC 42 /* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)] + (val40 & 1)*256*/ |
| 95 | |
| 96 | #define SPD_TREF 12 |