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review.coreboot.org / coreboot / 9631016660423d0585a1 / . / src / include / cpu / intel / l2_cache.h
blob: 587e43369f6f30c5be294bade91dd4f49539b468 [file] [log] [blame]
Keith Hui1ac19e22011-07-27 23:06:16 -0400[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010 Keith Hui <buurin@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Keith Hui1ac19e22011-07-27 23:06:16 -0400[diff] [blame]15 */
16
17/* The L2 cache definitions here only apply to SECC/SECC2 P6 family CPUs
18 * with Klamath (63x), Deschutes (65x) and Katmai (67x) cores.
19 * It is not required for Coppermine (68x) and Tualatin (6bx) cores.
20 * It is currently not known if Celerons with Mendocino core require
21 * the special initialization.
22 * Covington-core Celerons do not have L2 cache.
23 */
24
25/* This is a straight port from coreboot v1. */
26
27#ifndef __P6_L2_CACHE_H
28#define __P6_L2_CACHE_H
29
30#define IA32_PLATFORM_ID 0x17
31#define EBL_CR_POWERON 0x2A
32
33#define BBL_CR_D0 0x88
34#define BBL_CR_D1 0x89
35#define BBL_CR_D2 0x8A
36#define BBL_CR_D3 0x8B
37
38#define BBL_CR_ADDR 0x116
39#define BBL_CR_DECC 0x118
40#define BBL_CR_CTL 0x119
41#define BBL_CR_TRIG 0x11A
42#define BBL_CR_BUSY 0x11B
43#define BBL_CR_CTL3 0x11E
44
45#define BBLCR3_L2_CONFIGURED (1<<0)
46/* bits [4:1] */
47#define BBLCR3_L2_LATENCY 0x1e
48#define BBLCR3_L2_ECC_CHECK_ENABLE (1<<5)
49#define BBLCR3_L2_ADDR_PARITY_ENABLE (1<<6)
50#define BBLCR3_L2_CRTN_PARITY_ENABLE (1<<7)
51#define BBLCR3_L2_ENABLED (1<<8)
52/* bits [17:13] */
53#define BBLCR3_L2_SIZE (0x1f << 13)
54#define BBLCR3_L2_SIZE_256K (0x01 << 13)
55#define BBLCR3_L2_SIZE_512K (0x02 << 13)
56#define BBLCR3_L2_SIZE_1M (0x04 << 13)
57#define BBLCR3_L2_SIZE_2M (0x08 << 13)
58#define BBLCR3_L2_SIZE_4M (0x10 << 13)
59/* bits [22:20] */
60#define BBLCR3_L2_PHYSICAL_RANGE (0x7 << 20);
61/* TODO: This bitmask does not agree with Intel's documentation.
62 * Get confirmation one way or another.
63 */
64#define BBLCR3_L2_SUPPLIED_ECC 0x40000
65
66#define BBLCR3_L2_HARDWARE_DISABLE (1<<23)
67/* Also known as... */
68#define BBLCR3_L2_NOT_PRESENT (1<<23)
69
70/* L2 commands */
71#define L2CMD_RLU 0x0c /* 01100 Data read w/ LRU update */
72#define L2CMD_TRR 0x0e /* 01110 Tag read with data read */
73#define L2CMD_TI 0x0f /* 01111 Tag inquiry */
74#define L2CMD_CR 0x02 /* 00010 L2 control register read */
75#define L2CMD_CW 0x03 /* 00011 L2 control register write */
76#define L2CMD_TWR 0x08 /* 010-- Tag read w/ data read */
77#define L2CMD_TWW 0x1c /* 111-- Tag write w/ data write */
78#define L2CMD_TW 0x10 /* 100-- Tag write */
79/* MESI encode for L2 commands above */
80#define L2CMD_MESI_M 3
81#define L2CMD_MESI_E 2
82#define L2CMD_MESI_S 1
83#define L2CMD_MESI_I 0
84
85extern int calculate_l2_latency(void);
86extern int signal_l2(u32 address_low, u32 data_high, u32 data_low, int way, u8 command);
87extern int read_l2(u32 address);
88extern int write_l2(u32 address, u32 data);
89extern int test_l2_address_alias(u32 address1, u32 address2, u32 data_high, u32 data_low);
90extern int calculate_l2_cache_size(void);
91extern int calculate_l2_physical_address_range(void);
92extern int set_l2_ecc(void);
93
94extern int p6_configure_l2_cache(void);
95
96#endif /* __P6_L2_CACHE_H */