Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * Copyright (C) 2007 Advanced Micro Devices |
| 4 | * |
| 5 | */ |
| 6 | |
| 7 | #ifndef CPU_AMD_VR_H |
| 8 | #define CPU_AMD_VR_H |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 9 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 10 | #define VRC_INDEX 0xAC1C // Index register |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 11 | #define VRC_DATA 0xAC1E // Data register |
| 12 | #define VR_UNLOCK 0xFC53 // Virtual register unlock code |
| 13 | #define NO_VR -1 // No virtual registers |
| 14 | |
| 15 | #define VRC_MISCELLANEOUS 0x00 // Miscellaneous Class |
| 16 | #define VSA_VERSION_NUM 0x00 |
| 17 | #define HIGH_MEM_ACCESS 0x01 |
| 18 | #define GET_VSM_INFO 0x02 // Used by INFO |
| 19 | #define GET_BASICS 0x00 |
| 20 | #define GET_EVENT 0x01 |
| 21 | #define GET_STATISTICS 0x02 |
| 22 | #define GET_HISTORY 0x03 |
| 23 | #define GET_HARDWARE 0x04 |
| 24 | #define GET_ERROR 0x05 |
| 25 | #define SET_VSM_TYPE 0x06 |
| 26 | #define SIGNATURE 0x03 |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 27 | #define VSA2_SIGNATURE 0x56534132 // 'VSA2' returned in EAX |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 28 | |
| 29 | #define GET_HW_INFO 0x04 |
| 30 | #define VSM_VERSION 0x05 |
| 31 | #define CTRL_ALT_DEL 0x06 |
| 32 | #define MSR_ACCESS 0x07 |
| 33 | #define GET_DESCR_INFO 0x08 |
| 34 | #define PCI_INT_AB 0x09 // GPIO pins for INTA# and INTB# |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 35 | #define PCI_INT_CD 0x0A // GPIO pins for INTC# and INTD# |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 36 | #define WATCHDOG 0x0B // Watchdog timer |
| 37 | |
| 38 | #define MAX_MISC WATCHDOG |
| 39 | |
| 40 | |
| 41 | // NOTE: Do not change the order of the following registers: |
| 42 | #define VRC_AUDIO 0x01 // XpressAudio Class |
| 43 | #define AUDIO_VERSION 0x00 |
| 44 | #define PM_STATE 0x01 |
| 45 | #define SB_16_IO_BASE 0x02 |
| 46 | #define MIDI_BASE 0x03 |
| 47 | #define CPU_USAGE 0x04 |
| 48 | #define CODEC_TYPE 0x05 |
| 49 | #define STATE_INDEX 0x06 |
| 50 | #define STATE_DATA 0x07 |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 51 | #define AUDIO_IRQ 0x08 // For use by native audio drivers |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 52 | #define STATUS_PTR 0x09 // For use by native audio drivers |
| 53 | #define MAX_AUDIO STATUS_PTR |
| 54 | |
| 55 | #define VRC_VG 0x02 // SoftVG Class |
| 56 | #define VRC_VGA 0x02 // SoftVGA Class |
| 57 | #define VG_MEM_SIZE 0x00 // bits 7:0 - 512K unit size, bit 8 controller priority |
| 58 | #define VG_CONFIG 0x00 // Main configuration register |
| 59 | #define VG_CFG_BYPASS 0x0001 // DOTPLL bypass bit |
| 60 | #define VG_MEM_MASK 0x00FE // Memory size mask bits, 2MB increment |
| 61 | #define VG_CFG_DSMASK 0x0700 // Active display mask bits |
| 62 | #define VG_CFG_DSCRT 0x0000 // Active display is CRT |
| 63 | #define VG_CFG_DSPAN 0x0100 // Active display is panel |
| 64 | #define VG_CFG_DSTV 0x0200 // Active display is TV |
| 65 | #define VG_CFG_DSSIM 0x0400 // Simultaneous CRT |
| 66 | #define VG_CFG_PRIORITY 0x0800 // Controller priority bit |
| 67 | #define VG_CFG_MONO 0x1000 // External monochrome card support bit |
| 68 | #define VG_CFG_DRIVER 0x2000 // Driver active bit |
| 69 | #define VG_CRTC_DIAG 0x8000 // Enable CRTC emulation |
| 70 | |
| 71 | // Defined for GX3/GX3VG |
| 72 | #define VG_REFRESH 0x01 // Mode refresh, a mode switch without changing modes |
| 73 | #define VG_FRSH_REF_MASK 0xE000 // Refresh rate mask |
| 74 | #define VG_FRSH_REF_GO 0x1000 // Refresh rate GO bit |
| 75 | // Uses CFP_REF_xxx values from below |
| 76 | #define VG_FRSH_BPP_MASK 0x0E00 // Color depth mask |
| 77 | #define VG_FRSH_BPP_GO 0x0100 // Color depth GO bit |
| 78 | #define FRSH_BPP_8RGB 0x0200 // 8 bits per pixel, RGB |
| 79 | #define FRSH_BPP_16ARGB 0x0400 // 16BPP, ARGB (4:4:4:4) |
| 80 | #define FRSH_BPP_15RGB 0x0600 // 15BPP, RGB (1:5:5:5) |
| 81 | #define FRSH_BPP_16RGB 0x0800 // 16BPP, RGB (5:6:5) |
| 82 | #define FRSH_BPP_24RGB 0x0A00 // 24BPP, RGB (0:8:8:8) |
| 83 | #define FRSH_BPP_32ARGB 0x0C00 // 32BPP, ARGB (8:8:8:8) |
| 84 | #define VG_CFG_DPMS 0x00C0 // DPMS mask bits |
| 85 | #define VG_CFG_DPMS_H 0x0040 // HSYNC mask bit |
| 86 | #define VG_CFG_DPMS_V 0x0080 // VSYNC mask bit |
| 87 | #define VG_VESA_SV_RST 0x0020 // VESA Save/Restore state flag |
| 88 | #define VG_VESA_RST 0x0000 // VESA Restore state |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 89 | #define VG_VESA_SV 0x0020 // VESA Save state |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 90 | #define VG_FRSH_MODE 0x0002 // Mode refresh flag |
| 91 | #define VG_FRSH_TIMINGS 0x0001 // Timings only refresh flag |
| 92 | |
| 93 | // Defined for GX2/SoftVG |
| 94 | #define VG_PLL_REF 0x01 // PLL reference frequency selection register |
| 95 | #define PLL_14MHZ 0x0000 // 14.31818MHz PLL reference frequency (Default) |
| 96 | #define PLL_48MHZ 0x0100 // 48MHz PLL reference frequency |
| 97 | |
| 98 | // Defined for GX1/SoftVGA |
| 99 | #define VGA_MEM_SIZE 0x01 // bits 7:1 - 128K unit size, bit 0 controller enable |
| 100 | |
| 101 | #define VG_FP_TYPE 0x02 // Flat panel type data |
| 102 | // VG_FP_TYPE definitions for GX2/SoftVG |
| 103 | #define FP_TYPE_SSTN 0x0000 // SSTN panel type value |
| 104 | #define FP_TYPE_DSTN 0x0001 // DSTN panel type value |
| 105 | #define FP_TYPE_TFT 0x0002 // TFT panel type value |
| 106 | #define FP_TYPE_LVDS 0x0003 // LVDS panel type value |
| 107 | #define FP_RES_6X4 0x0000 // 640x480 resolution value |
| 108 | #define FP_RES_8X6 0x0008 // 800x600 resolution value |
| 109 | #define FP_RES_10X7 0x0010 // 1024x768 resolution value |
| 110 | #define FP_RES_11X8 0x0018 // 1152x864 resolution value |
| 111 | #define FP_RES_12X10 0x0020 // 1280x1024 resolution value |
| 112 | #define FP_RES_16X12 0x0028 // 1600x1200 resolution value |
| 113 | #define FP_WIDTH_8 0x0000 // 8 bit data bus width |
| 114 | #define FP_WIDTH_9 0x0040 // 9 bit data bus width |
| 115 | #define FP_WIDTH_12 0x0080 // 12 bit data bus width |
| 116 | #define FP_WIDTH_18 0x00C0 // 18 bit data bus width |
| 117 | #define FP_WIDTH_24 0x0100 // 24 bit data bus width |
| 118 | #define FP_WIDTH_16 0x0140 // 16 bit data bus width - 16 bit Mono DSTN only |
| 119 | #define FP_COLOR_COLOR 0x0000 // Color panel |
| 120 | #define FP_COLOR_MONO 0x0200 // Mono Panel |
| 121 | #define FP_PPC_1PPC 0x0000 // One pixel per clock |
| 122 | #define FP_PPC_2PPC 0x0400 // Two pixels per clock |
| 123 | #define FP_H_POL_LGH 0x0000 // HSync at panel, normally low, active high |
| 124 | #define FP_H_POL_HGL 0x0800 // HSync at panel, normally high, active low |
| 125 | #define FP_V_POL_LGH 0x0000 // VSync at panel, normally low, active high |
| 126 | #define FP_V_POL_HGL 0x1000 // VSync at panel, normally high, active low |
| 127 | #define FP_REF_60 0x0000 // 60Hz refresh rate |
| 128 | #define FP_REF_65 0x2000 // 65Hz refresh rate |
| 129 | #define FP_REF_70 0x4000 // 70Hz refresh rate |
| 130 | #define FP_REF_72 0x6000 // 72Hz refresh rate |
| 131 | #define FP_REF_75 0x8000 // 75Hz refresh rate |
| 132 | #define FP_REF_85 0xA000 // 85Hz refresh rate |
| 133 | |
| 134 | // VG_FP_TYPE definitions for GX3/GX3VG |
| 135 | #define FP_TYPE_TYPE 0x0003 // Flat panel type bits mask |
| 136 | #define CFP_TYPE_TFT 0x0000 // TFT panel type value |
| 137 | #define CFP_TYPE_LVDS 0x0001 // LVDS panel type value |
| 138 | #define FP_TYPE_RES 0x0038 // Panel resolution bits mask |
| 139 | #define CFP_RES_3X2 0x0000 // 320x240 resolution value |
| 140 | #define CFP_RES_6X4 0x0008 // 640x480 resolution value |
| 141 | #define CFP_RES_8X6 0x0010 // 800x600 resolution value |
| 142 | #define CFP_RES_10X7 0x0018 // 1024x768 resolution value |
| 143 | #define CFP_RES_11X8 0x0020 // 1152x864 resolution value |
| 144 | #define CFP_RES_12X10 0x0028 // 1280x1024 resolution value |
| 145 | #define CFP_RES_16X12 0x0030 // 1600x1200 resolution value |
| 146 | #define FP_TYPE_BUS 0x00C0 // Data bus width and pixels/clock mask |
| 147 | #define CFP_BUS_1PPC 0x0040 // 9, 12, 18 or 24 bit data bus, 1 pixel per clock |
| 148 | #define CFP_BUS_2PPC 0x0080 // 18 or 24 bit data bus, 2 pixels per clock |
| 149 | #define FP_TYPE_HPOL 0x0800 // HSYNC polarity into the panel |
| 150 | #define CFP_HPOL_HGL 0x0000 // HSync at panel, normally high, active low |
| 151 | #define CFP_HPOL_LGH 0x0800 // HSync at panel, normally low, active high |
| 152 | #define FP_TYPE_VPOL 0x1000 // VSYNC polarity into the panel |
| 153 | #define CFP_VPOL_HGL 0x0000 // VSync at panel, normally high, active low |
| 154 | #define CFP_VPOL_LGH 0x1000 // VSync at panel, normally low, active high |
| 155 | #define FP_TYPE_REF 0xE000 // Panel refresh rate |
| 156 | #define CFP_REF_60 0x0000 // 60Hz refresh rate |
| 157 | #define CFP_REF_70 0x2000 // 70Hz refresh rate |
| 158 | #define CFP_REF_75 0x4000 // 75Hz refresh rate |
| 159 | #define CFP_REF_85 0x6000 // 85Hz refresh rate |
| 160 | #define CFP_REF_100 0x8000 // 100Hz refresh rate |
| 161 | |
| 162 | #define VG_FP_OPTION 0x03 // Flat panel option data |
| 163 | #define FP_OPT_SCLK_NORMAL 0x0000 // SHFTClk not inverted to panel |
| 164 | #define FP_OPT_SCLK_INVERTED 0x0010 // SHFTClk inverted to panel |
| 165 | #define FP_OPT_SCLK_ACT_ACTIVE 0x0000 // SHFTClk active during "active" only |
| 166 | #define FP_OPT_SCLK_ACT_FREE 0x0020 // SHFTClk free-running |
| 167 | #define FP_OPT_LP_ACT_FREE 0x0000 // LP free-running |
| 168 | #define FP_OPT_LP_ACT_ACTIVE 0x0040 // LP active during "active" only |
| 169 | #define FP_OPT_LDE_POL_LGH 0x0000 // LDE/MOD, normally low, active high |
| 170 | #define FP_OPT_LDE_POL_HGL 0x0080 // LDE/MOD, normally high, active low |
| 171 | #define FP_OPT_PWR_DLY_32MS 0x0000 // 32MS delay for each step of pwr seq. |
| 172 | #define FP_OPT_PWR_DLY_128MS 0x0100 // 128MS delay for each step of pwr seq. |
| 173 | |
| 174 | #define VG_TV_CONFIG 0x04 // TV configuration register |
| 175 | #define VG_TV_ENC 0x000F // TV encoder select mask |
| 176 | #define VG_TV_ADV7171 0x0000 // ADV7171 Encoder |
| 177 | #define VG_TV_SAA7127 0x0001 // ADV7171 Encoder |
| 178 | #define VG_TV_ADV7300 0x0002 // ADV7300 Encoder |
| 179 | #define VG_TV_FS454 0x0003 // FS454 Encoder |
| 180 | #define VG_TV_FMT 0x0070 // TV encoder output format mask |
| 181 | #define VG_TV_FMT_SHIFT 0x0004 // Right shift value |
| 182 | #define VG_TV_NTSC 0x0000 // NTSC output format |
| 183 | #define VG_TV_PAL 0x0010 // PAL output format |
| 184 | #define VG_TV_HDTV 0x0020 // HDTV output format |
| 185 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 186 | // The meaning of the VG_TV_RES field is dependent on the selected |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 187 | // encoder and output format. The translations are: |
| 188 | // ADV7171 - Not Used |
| 189 | // SAA7127 - Not Used |
| 190 | // ADV7300 - HDTV resolutions only |
| 191 | // LO -> 720x480p |
| 192 | // MED -> 1280x720p |
| 193 | // HI -> 1920x1080i |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 194 | // FS454 - Both SD and HD resolutions |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 195 | // SD Resolutions - NTSC and PAL |
| 196 | // LO -> 640x480 |
| 197 | // MED -> 800x600 |
| 198 | // HI -> 1024x768 |
| 199 | // HD Resolutions |
| 200 | // LO -> 720x480p |
| 201 | // MED -> 1280x720p |
| 202 | // HI -> 1920x1080i |
| 203 | #define VG_TV_RES 0x0780 // TV resolution select mask |
| 204 | #define VG_TV_RES_SHIFT 0x0007 // Right shift value |
| 205 | #define VG_TV_RES_LO 0x0000 // Low resolution |
| 206 | #define VG_TV_RES_MED 0x0080 // Medium resolution |
| 207 | #define VG_TV_RES_HI 0x0100 // High resolution |
| 208 | #define VG_TV_PASSTHRU 0x0800 // TV passthru mode |
| 209 | |
| 210 | #define VG_TV_SCALE_ADJ 0x05 // Modifies scaling factors for TV resolutions |
| 211 | #define VG_TV_HACT_ADJ 0x00FF // Horizontal active scale adjust value mask |
| 212 | #define VG_TV_VACT_ADJ 0xFF00 // Vertical active scale adjust value mask |
| 213 | |
| 214 | #define VG_DEBUG 0x0F // A debug register |
| 215 | |
| 216 | #define VG_FT_HTOT 0x10 // Fixed timings, horizontal total |
| 217 | #define VG_FT_HACT 0x11 // Fixed timings, horizontal active |
| 218 | #define VG_FT_HBST 0x12 // Fixed timings, horizontal blank start |
| 219 | #define VG_FT_HBND 0x13 // Fixed timings, horizontal blank end |
| 220 | #define VG_FT_HSST 0x14 // Fixed timings, horizontal sync start |
| 221 | #define VG_FT_HSND 0x15 // Fixed timings, horizontal sync end |
| 222 | |
| 223 | #define VG_FT_VTOT 0x16 // Fixed timings, vertical total |
| 224 | #define VG_FT_VACT 0x17 // Fixed timings, vertical active |
| 225 | #define VG_FT_VBST 0x18 // Fixed timings, vertical blank start |
| 226 | #define VG_FT_VBND 0x19 // Fixed timings, vertical blank end |
| 227 | #define VG_FT_VSST 0x1A // Fixed timings, vertical sync start |
| 228 | #define VG_FT_VSND 0x1B // Fixed timings, vertical sync end |
| 229 | |
| 230 | #define VG_START_OFFS_LO 0x20 // Framebuffer start offset bits 15:0 |
| 231 | #define VG_START_OFFS_HI 0x21 // Framebuffer start offset bits 27:16 |
| 232 | |
| 233 | #define VG_FT_VEACT 0x28 // Fixed timings, vertical active |
| 234 | #define VG_FT_VETOT 0x29 // Fixed timings, vertical total |
| 235 | #define VG_FT_VEBST 0x2A // Fixed timings, vertical blank start |
| 236 | #define VG_FT_VEBND 0x2B // Fixed timings, vertical blank end |
| 237 | #define VG_FT_VESST 0x2C // Fixed timings, vertical sync start |
| 238 | #define VG_FT_VESND 0x2D // Fixed timings, vertical sync end |
| 239 | |
| 240 | #define MAX_VGA VGA_MEM_SIZE |
| 241 | // #define MAX_VG VG_FP_OPTION |
| 242 | // #define MAX_VG VG_START_OFFS_HI |
| 243 | #define MAX_VG VG_FT_VESND |
| 244 | |
| 245 | #define VRC_APM 0x03 |
| 246 | #define REPORT_EVENT 0x00 |
| 247 | #define CAPABILITIES 0x01 |
| 248 | #define APM_PRESENT 0x02 |
| 249 | #define MAX_APM APM_PRESENT |
| 250 | |
| 251 | |
| 252 | #define VRC_PM 0x04 // Legacy PM Class |
| 253 | #define POWER_MODE 0x00 |
| 254 | #define POWER_STATE 0x01 |
| 255 | #define DOZE_TIMEOUT 0x02 |
| 256 | #define STANDBY_TIMEOUT 0x03 |
| 257 | #define SUSPEND_TIMEOUT 0x04 |
| 258 | #define PS2_TIMEOUT 0x05 |
| 259 | #define RESUME_ON_RING 0x06 |
| 260 | #define VIDEO_TIMEOUT 0x07 |
| 261 | #define DISK_TIMEOUT 0x08 |
| 262 | #define FLOPPY_TIMEOUT 0x09 |
| 263 | #define SERIAL_TIMEOUT 0x0A |
| 264 | #define PARALLEL_TIMEOUT 0x0B |
| 265 | #define IRQ_WAKEUP_MASK 0x0C |
| 266 | // #define SUSPEND_MODULATION 0x0D |
| 267 | #define SLEEP_PIN 0x0E |
| 268 | #define SLEEP_PIN_ATTR 0x0F |
| 269 | // #define SMI_WAKEUP_MASK 0x10 |
| 270 | #define INACTIVITY_CONTROL 0x11 |
| 271 | #define PM_S1_CLOCKS 0x12 |
| 272 | #define S1_CLOCKS_ON 0x00 |
| 273 | #define S1_CLOCKS_OFF 0x01 |
| 274 | // #define PM_S2_CLOCKS 0x13 |
| 275 | // #define PM_S3_CLOCKS 0x14 |
| 276 | // #define PM_S4_CLOCKS 0x15 |
| 277 | // #define PM_S5_CLOCKS 0x16 |
| 278 | #define PM_S0_LED 0x17 |
| 279 | #define PM_S1_LED 0x18 |
| 280 | #define PM_S2_LED 0x19 |
| 281 | #define PM_S3_LED 0x1A |
| 282 | #define PM_S4_LED 0x1B |
| 283 | #define PM_S5_LED 0x1C |
| 284 | #define PM_LED_GPIO 0x1D |
| 285 | #define PM_IMM_LED 0x1E |
| 286 | #define PM_PWR_LEDS 0x1F |
| 287 | #define MB_LED0 0x01 |
| 288 | #define MB_LED1 0x02 |
| 289 | #define MB_LED2 0x04 |
| 290 | #define MB_LED3 0x08 |
| 291 | #define SIO_LED0 0x10 |
| 292 | #define SIO_LED1 0x20 |
| 293 | #define SIO_LED2 0x40 |
| 294 | #define SIO_LED3 0x80 |
| 295 | #define PM_PME_MASK 0x20 |
| 296 | #define MAX_PM PM_PME_MASK |
| 297 | |
| 298 | |
| 299 | #define VRC_INFRARED 0x05 |
| 300 | #define MAX_INFRARED NO_VR |
| 301 | |
| 302 | #define VRC_TV 0x06 // TV Encoder Class |
| 303 | #define TV_ENCODER_TYPE 0x00 |
| 304 | #define TV_CALLBACK_MASK 0x01 |
| 305 | #define TV_MODE 0x02 |
| 306 | #define TV_POSITION 0x03 |
| 307 | #define TV_BRIGHTNESS 0x04 |
| 308 | #define TV_CONTRAST 0x05 |
| 309 | #define TV_OUTPUT 0x06 |
| 310 | #define TV_TIMING 0x10 // 0x10...0x1D are all timings |
| 311 | #define MAX_TV TV_TIMING |
| 312 | |
| 313 | |
| 314 | |
| 315 | #define VRC_EXTERNAL_AMP 0x07 |
| 316 | #define EAPD_VERSION 0x00 |
| 317 | #define AMP_POWER 0x01 |
| 318 | #define AMP_OFF 0x00 |
| 319 | #define AMP_ON 0x01 |
| 320 | #define AMP_TYPE 0x02 |
| 321 | #define MAX_EXTERNAL_AMP AMP_TYPE |
| 322 | |
| 323 | |
| 324 | #define VRC_ACPI 0x08 |
| 325 | #define ENABLE_ACPI 0x00 // Enable ACPI Mode |
| 326 | #define SCI_IRQ 0x01 // Set the IRQ the SCI is mapped to, sysbios use. |
| 327 | #define ACPINVS_LO 0x02 // new calls to send 32bit physAddress of |
| 328 | #define ACPINVS_HI 0x03 // ACPI NVS region to VSA |
| 329 | #define GLOBAL_LOCK 0x04 // read requests semaphore, write clears |
| 330 | #define ACPI_UNUSED1 0x05 |
| 331 | #define RW_PIRQ 0x06 // read/write PCI IRQ router regs in SB Func0 cfg space |
| 332 | #define SLPB_CLEAR 0x07 // clear sleep button GPIO status's |
| 333 | #define PIRQ_ROUTING 0x08 // read the PCI IRQ routing based on BIOS setup |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 334 | #define ACPI_UNUSED2 0x09 |
| 335 | #define ACPI_UNUSED3 0x0A |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 336 | #define PIC_INTERRUPT 0x0B |
| 337 | #define ACPI_PRESENT 0x0C |
| 338 | #define ACPI_GEN_COMMAND 0x0D |
| 339 | #define ACPI_GEN_PARAM1 0x0E |
| 340 | #define ACPI_GEN_PARAM2 0x0F |
| 341 | #define ACPI_GEN_PARAM3 0x10 |
| 342 | #define ACPI_GEN_RETVAL 0x11 |
| 343 | #define MAX_ACPI ACPI_GEN_RETVAL |
| 344 | |
| 345 | #define VRC_ACPI_OEM 0x09 |
| 346 | #define MAX_ACPI_OEM NO_VR |
| 347 | |
| 348 | #define VRC_POWER 0x0A |
| 349 | #define BATTERY_UNITS 0x00 // No. battery units |
| 350 | #define BATTERY_SELECT 0x01 |
| 351 | #define AC_STATUS 0x02 |
| 352 | #define BATTERY_STATUS 0x03 |
| 353 | #define BATTERY_FLAG 0x04 |
| 354 | #define BATTERY_PERCENTAGE 0x05 |
| 355 | #define BATTERY_TIME 0x06 |
| 356 | #define MAX_POWER BATTERY_TIME |
| 357 | |
| 358 | |
| 359 | |
| 360 | #define VRC_OHCI 0x0B // OHCI Class |
| 361 | #define SET_LED 0x00 |
| 362 | #define INIT_OHCI 0x01 |
| 363 | #define MAX_OHCI INIT_OHCI |
| 364 | |
| 365 | #define VRC_KEYBOARD 0x0C // Kbd Controller Class |
| 366 | #define KEYBOARD_PRESENT 0x00 |
| 367 | #define SCANCODE 0x01 |
| 368 | #define MOUSE_PRESENT 0x02 |
| 369 | #define MOUSE_BUTTONS 0x03 |
| 370 | #define MOUSE_XY 0x04 |
| 371 | #define MAX_KEYBOARD MOUSE_XY |
| 372 | |
| 373 | |
| 374 | #define VRC_DDC 0x0D // Video DDC Class |
| 375 | #define VRC_DDC_ENABLE 0x00 // Enable/disable register |
| 376 | #define DDC_DISABLE 0x00 |
| 377 | #define DDC_ENABLE 0x01 |
| 378 | #define VRC_DDC_IO 0x01 // A non-zero value for safety |
| 379 | #define MAX_DDC VRC_DDC_IO |
| 380 | |
| 381 | #define VRC_DEBUGGER 0x0E |
| 382 | #define MAX_DEBUGGER NO_VR |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 383 | |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 384 | |
| 385 | #define VRC_STR 0x0F // Virtual Register class |
| 386 | #define RESTORE_ADDR 0x00 // Physical address of MSR restore table |
| 387 | |
| 388 | |
| 389 | #define VRC_COP8 0x10 // Virtual Register class |
| 390 | #define VRC_HIB_ENABLE 0x00 // HIB enable/disable index |
| 391 | #define HIB_ENABLE 0x00 // HIB enable command |
| 392 | #define HIB_DISABLE 0x01 // HIB disable command |
| 393 | #define VRC_HIB_SEND 0x01 // Send packet to COP8 |
| 394 | #define VRC_HIB_READUART 0x02 // Read byte from COP8 UART |
| 395 | #define VRC_HIB_VERSION 0x03 // Read COP8 version |
| 396 | #define VRC_HIB_SERIAL 0x04 // Read 8 byte serial number |
| 397 | #define VRC_HIB_USRBTN 0x05 // Read POST button pressed status |
| 398 | #define MAX_COP8 NO_VR |
| 399 | |
| 400 | #define VRC_OWL 0x11 // Virtual Register class |
| 401 | #define VRC_OWL_DAC 0x00 // DAC (Backlight) Control |
| 402 | #define VRC_OWL_GPIO 0x01 // GPIO Control |
| 403 | #define MAX_OWL VRC_OWL_GPIO |
| 404 | |
| 405 | #define VRC_SYSINFO 0x12 // Virtual Register class |
| 406 | #define VRC_SI_VERSION 0x00 // Sysinfo VSM version |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 407 | #define VRC_SI_CPU_MHZ 0x01 // CPU speed in MHZ |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 408 | #define VRC_SI_CHIPSET_BASE_LOW 0x02 |
| 409 | #define VRC_SI_CHIPSET_BASE_HI 0x03 |
| 410 | #define VRC_SI_CHIPSET_ID 0x04 |
| 411 | #define VRC_SI_CHIPSET_REV 0x05 |
| 412 | #define VRC_SI_CPU_ID 0x06 |
| 413 | #define VRC_SI_CPU_REV 0x07 |
| 414 | #define MAX_SYSINFO VRC_SI_CPU_REV |
| 415 | |
| 416 | #define VRC_SUPERIO 0x13 |
| 417 | #define VRC_SIO_CHIPID 0x00 |
| 418 | #define VRC_SIO_NUMLD 0x01 |
| 419 | #define VRC_SIO_FDCEN 0x02 |
| 420 | #define VRC_SIO_FDCIO 0x03 |
| 421 | #define VRC_SIO_FDCIRQ 0x04 |
| 422 | #define VRC_SIO_FDCDMA 0x05 |
| 423 | #define VRC_SIO_FDCCFG1 0x06 |
| 424 | #define VRC_SIO_FDCCFG2 0x07 |
| 425 | #define VRC_SIO_PP1EN 0x08 |
| 426 | #define VRC_SIO_PP1IO 0x09 |
| 427 | #define VRC_SIO_PP1IRQ 0x0A |
| 428 | #define VRC_SIO_PP1DMA 0x0B |
| 429 | #define VRC_SIO_PP1CFG1 0x0C |
| 430 | #define VRC_SIO_SP1EN 0x0D |
| 431 | #define VRC_SIO_SP1IO 0x0E |
| 432 | #define VRC_SIO_SP1IRQ 0x0F |
| 433 | #define VRC_SIO_SP1CFG1 0x10 |
| 434 | #define VRC_SIO_SP2EN 0x11 |
| 435 | #define VRC_SIO_SP2IO 0x12 |
| 436 | #define VRC_SIO_SP2IRQ 0x13 |
| 437 | #define VRC_SIO_SP2CFG1 0x14 |
| 438 | #define VRC_SIO_KBEN 0x15 |
| 439 | #define VRC_SIO_KBIO1 0x16 |
| 440 | #define VRC_SIO_KBIO2 0x17 |
| 441 | #define VRC_SIO_KBIRQ 0x18 |
| 442 | #define VRC_SIO_KBCFG1 0x19 |
| 443 | #define VRC_SIO_MSEN 0x1A |
| 444 | #define VRC_SIO_MSIO 0x1B |
| 445 | #define VRC_SIO_MSIRQ 0x1C |
| 446 | #define VRC_SIO_RTCEN 0x1D |
| 447 | #define VRC_SIO_RTCIO1 0x1E |
| 448 | #define VRC_SIO_RTCIO2 0x1F |
| 449 | #define VRC_SIO_RTCIRQ 0x20 |
| 450 | #define VRC_SIO_RTCCFG1 0x21 |
| 451 | #define VRC_SIO_RTCCFG2 0x22 |
| 452 | #define VRC_SIO_RTCCFG3 0x23 |
| 453 | #define VRC_SIO_RTCCFG4 0x24 |
| 454 | #define MAX_SUPERIO VRC_SIO_RTCCFG4 |
| 455 | |
| 456 | #define VRC_CHIPSET 0x14 |
| 457 | #define VRC_CS_PWRBTN 0x00 |
| 458 | #define VRC_CS_UART1 0x01 |
| 459 | #define VRC_CS_UART2 0x02 |
| 460 | #define MAX_CHIPSET VRC_CS_UART2 |
| 461 | |
| 462 | #define VRC_THERMAL 0x15 |
| 463 | #define VRC_THERMAL_CURR_RTEMP 0x00 // read only |
| 464 | #define VRC_THERMAL_CURR_LTEMP 0x01 // read only |
| 465 | #define VRC_THERMAL_FAN 0x02 |
| 466 | #define VRC_THERMAL_LOW_THRESHOLD 0x03 |
| 467 | #define VRC_THERMAL_HIGH_THRESHOLD 0x04 |
| 468 | #define VRC_THERMAL_INDEX 0x05 |
| 469 | #define VRC_THERMAL_DATA 0x06 |
| 470 | #define VRC_THERMAL_SMB_ADDRESS 0x07 |
| 471 | #define VRC_THERMAL_SMB_INDEX 0x08 |
| 472 | #define VRC_THERMAL_SMB_DATA 0x09 |
| 473 | #define MAX_THERMAL VRC_THERMAL_SMB_DATA |
| 474 | |
| 475 | #define MAX_VR_CLASS VRC_THERMAL |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 476 | |
| 477 | /* |
| 478 | * Write to a Virtual Register |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 479 | */ |
| 480 | static inline void vrWrite(uint16_t wClassIndex, uint16_t wData) |
| 481 | { |
| 482 | outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX); |
| 483 | outw(wData, VRC_DATA); |
| 484 | } |
| 485 | |
| 486 | /* |
| 487 | * Read from a Virtual Register |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 488 | * Returns a 16-bit word of data |
| 489 | */ |
| 490 | static inline uint16_t vrRead(uint16_t wClassIndex) |
| 491 | { |
| 492 | uint16_t wData; |
| 493 | outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX); |
| 494 | wData = inw(VRC_DATA); |
| 495 | return wData; |
| 496 | } |
| 497 | #endif |