blob: 8d3777e3264dd8113571c8d7d90b62858624607e [file] [log] [blame]
Kerry Shehd3e990c2012-02-07 20:31:35 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Kerry Shehd3e990c2012-02-07 20:31:35 +080014 */
15
16#ifndef CPU_AMD_FAM15_H
17#define CPU_AMD_FAM15_H
18
19#include <cpu/x86/msr.h>
20
21#define MCI_STATUS 0x00000401
Alexandru Gagniuc53072d82014-04-12 21:57:18 -050022#define MSR_SMM_BASE 0xC0010111
23#define MSR_SMM_MASK 0xC0010113
Kerry Shehd3e990c2012-02-07 20:31:35 +080024#define HWCR_MSR 0xC0010015
25#define NB_CFG_MSR 0xC001001f
26
27#define LS_CFG_MSR 0xC0011020
28#define IC_CFG_MSR 0xC0011021
29#define DC_CFG_MSR 0xC0011022
30#define CU_CFG_MSR 0xC0011023
31#define CU_CFG2_MSR 0xC001102A
32
33#define CPU_ID_FEATURES_MSR 0xC0011004
34#define CPU_ID_EXT_FEATURES_MSR 0xC0011005
35
zbao2c08f6a2012-07-02 15:32:58 +080036#if defined(__PRE_RAM__)
37void wait_all_core0_started(void);
38void wait_all_other_cores_started(u32 bsp_apicid);
39void wait_all_aps_started(u32 bsp_apicid);
40void allow_all_aps_stop(u32 bsp_apicid);
41#endif
42u32 get_initial_apicid(void);
43void get_bus_conf(void);
Kerry Shehd3e990c2012-02-07 20:31:35 +080044
45#endif /* CPU_AMD_FAM15_H */