| efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #ifndef CPU_AMD_FAM12_H |
| 17 | #define CPU_AMD_FAM12_H |
| 18 | |
| 19 | #include <cpu/x86/msr.h> |
| 20 | |
| 21 | #define HWCR_MSR 0xC0010015 |
| 22 | #define NB_CFG_MSR 0xC001001f |
| 23 | #define LS_CFG_MSR 0xC0011020 |
| 24 | #define IC_CFG_MSR 0xC0011021 |
| 25 | #define DC_CFG_MSR 0xC0011022 |
| 26 | #define BU_CFG_MSR 0xC0011023 |
| 27 | #define BU_CFG2_MSR 0xC001102A |
| 28 | |
| 29 | #define CPU_ID_FEATURES_MSR 0xC0011004 |
| Paul Menzel | 8048e74 | 2013-05-13 18:22:23 +0200 | [diff] [blame] | 30 | #define CPU_ID_EXT_FEATURES_MSR 0xC0011005 |
| efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 31 | |
| efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 32 | #if defined(__PRE_RAM__) |
| 33 | void wait_all_core0_started(void); |
| 34 | void wait_all_other_cores_started(u32 bsp_apicid); |
| 35 | void wait_all_aps_started(u32 bsp_apicid); |
| 36 | void allow_all_aps_stop(u32 bsp_apicid); |
| 37 | #endif |
| efdesign98 | 83d59b9 | 2011-09-15 11:24:29 -0600 | [diff] [blame] | 38 | void get_bus_conf(void); |
| efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 39 | |
| 40 | #endif /* CPU_AMD_FAM12_H */ |