Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | /* |
| 17 | * EC communication interface for QUANTA EnE KB3940Q Embedded Controller. |
| 18 | */ |
| 19 | |
| 20 | #ifndef _EC_QUANTA_ENE_KB3940Q_EC_H |
| 21 | #define _EC_QUANTA_ENE_KB3940Q_EC_H |
| 22 | |
| 23 | #define EC_IO 0x380 /* Mainboard specific. Could be Kconfig option */ |
| 24 | #define EC_IO_HIGH EC_IO + 1 |
| 25 | #define EC_IO_LOW EC_IO + 2 |
| 26 | #define EC_IO_DATA EC_IO + 3 |
| 27 | |
| 28 | |
| 29 | |
| 30 | // 60h/64h Command Interface |
| 31 | #define KBD_DATA 0x60 |
| 32 | #define KBD_COMMAND 0x64 |
| 33 | #define KBD_STATUS 0x64 |
| 34 | #define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) |
| 35 | #define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) |
| 36 | |
| 37 | // 62h/66h Command Interface |
| 38 | #define EC_DATA 0x62 |
| 39 | #define EC_COMMAND 0x66 |
| 40 | #define EC_SC 0x66 |
| 41 | |
| 42 | /* Wait 400ms for keyboard controller answers */ |
| 43 | #define KBC_TIMEOUT_IN_MS 400 |
| 44 | |
| 45 | u8 ec_kbc_read_ob(void); |
| 46 | void ec_kbc_write_cmd(u8 cmd); |
| 47 | void ec_kbc_write_ib(u8 data); |
| 48 | u8 ec_read_ob(void); |
| 49 | void ec_write_cmd(u8 cmd); |
| 50 | void ec_write_ib(u8 data); |
| 51 | |
| 52 | u8 ec_mem_read(u8 addr); |
| 53 | void ec_mem_write(u8 addr, u8 data); |
| 54 | |
| 55 | /***************************************************************************** |
| 56 | * EC Internal memory |
| 57 | */ |
| 58 | |
| 59 | #define EC_BAT_DCAP_LO 0x40 |
| 60 | #define EC_BAT_DCAP_HI 0x41 |
| 61 | #define EC_BAT_DVOLT_LO 0x42 |
| 62 | #define EC_BAT_DVOLT_HI 0x43 |
| 63 | #define EC_BAT_FULL_CAP_LO 0x44 |
| 64 | #define EC_BAT_FULL_CAP_HI 0x45 |
| 65 | #define EC_BAT_RATE_LO 0x46 |
| 66 | #define EC_BAT_RATE_HI 0x47 |
| 67 | #define EC_BAT_RMC_LO 0x48 |
| 68 | #define EC_BAT_RMC_HI 0x49 |
| 69 | #define EC_BAT_VOLT_LO 0x4A |
| 70 | #define EC_BAT_VOLT_HI 0x4B |
| 71 | #define EC_BAT_CHRG_CURT_LO 0x4C |
| 72 | #define EC_BAT_CHRG_CURT_HI 0x4D |
| 73 | #define EC_BAT_CHRG_VOLT_LO 0x4E |
| 74 | #define EC_BAT_CHRG_VOLT_HI 0x4F |
| 75 | #define EC_BAT_TEMP_LO 0x50 |
| 76 | #define EC_BAT_TEMP_HI 0x51 |
| 77 | #define EC_BAT_SN_LO 0x52 |
| 78 | #define EC_BAT_SN_HI 0x53 |
| 79 | #define EC_BAT_RSOC_LO 0x54 |
| 80 | #define EC_BAT_RSOC_HI 0x55 |
| 81 | #define EC_BAT_STATUS_LO 0x56 |
| 82 | #define EC_BAT_STATUS_HI 0x57 |
| 83 | #define EC_BAT_CYCLE_COUNT_LO 0x58 |
| 84 | #define EC_BAT_CYCLE_COUNT_HI 0x59 |
| 85 | #define EC_BAT_MFG_DATE_LO 0x5A |
| 86 | #define EC_BAT_MFG_DATE_HI 0x5B |
| 87 | #define EC_BAT_CHEMISTRY0 0x60 |
| 88 | #define EC_BAT_CHEMISTRY1 0x61 |
| 89 | #define EC_BAT_CHEMISTRY2 0x62 |
| 90 | #define EC_BAT_CHEMISTRY3 0x63 |
| 91 | #define EC_BAT_DEVICE_NAME0 0x64 |
| 92 | #define EC_BAT_DEVICE_NAME1 0x65 |
| 93 | #define EC_BAT_DEVICE_NAME2 0x66 |
| 94 | #define EC_BAT_DEVICE_NAME3 0x67 |
| 95 | #define EC_BAT_DEVICE_NAME4 0x68 |
| 96 | #define EC_BAT_DEVICE_NAME5 0x69 |
| 97 | #define EC_BAT_DEVICE_NAME6 0x6A |
| 98 | |
| 99 | #define EC_POWER_FLAG 0x70 |
| 100 | #define EC_PF_ADAPTER_IN (1 << 0) |
| 101 | #define EC_PF_ADAPTER_PIN (1 << 1) |
| 102 | #define EC_PF_BATT_IN (1 << 2) |
| 103 | #define EC_PF_BATT_DESTROY (1 << 3) |
| 104 | #define EC_PF_ACPI_MODE (1 << 4) |
| 105 | #define EC_PF_X86_BIOS (1 << 6) |
| 106 | #define EC_PF_COREBOOT 0 |
| 107 | #define EC_PF_PASSIVE_THERM (1 << 7) |
| 108 | |
| 109 | #define EC_CHARGER_STATUS 0x71 |
| 110 | #define EC_CHS_BAT_DISCHARGING (1 << 0) |
| 111 | #define EC_CHS_BAT_CHARGING (1 << 1) |
| 112 | #define EC_CHS_BAT_CRITICAL (1 << 2) |
| 113 | |
| 114 | #define EC_HW_GPI_STATUS 0x72 |
| 115 | #define EC_GPI_LID_STAT_BIT 0 |
| 116 | #define EC_GPI_RECOVERY_MODE_BIT 1 |
| 117 | #define EC_GPI_LID_OPEN (1 << EC_GPI_LID_STAT_BIT) |
| 118 | #define EC_GPI_RECOVERY_STATUS (1 << EC_GPI_RECOVERY_MODE_BIT) |
| 119 | |
| 120 | #define EC_GPIO_STATUS 0x73 |
| 121 | #define EC_GPIO_TP_LED_ENABLE (1 << 0) |
| 122 | #define EC_GPIO_TP_LED_STATUS (1 << 1) |
| 123 | |
| 124 | #define EC_CPU_TMP 0x78 |
| 125 | #define EC_GPU_TMP 0x79 |
| 126 | #define EC_LOCAL_TMP1 0x7A |
| 127 | #define EC_LOCAL_TMP2 0x7B |
| 128 | #define EC_FAN_TACH_LO 0x7C |
| 129 | #define EC_FAN_TACH_HI 0x7D |
| 130 | #define EC_FAN_DBG_RPM_LO 0x7E |
| 131 | #define EC_FAN_DBG_RPM_HI 0x7F |
| 132 | |
| 133 | #define EC_KBID_REG 0x80 |
| 134 | #define EC_KBD_EN 0 |
| 135 | #define EC_KBD_JP (1 << 1) |
| 136 | #define EC_CURR_PS 0x81 |
| 137 | #define EC_MAX_PS 0x82 |
| 138 | |
| 139 | #define EC_EC_PSW 0x83 |
| 140 | #define EC_PSW_IKB (1 << 0) |
| 141 | #define EC_PSW_TP (1 << 1) |
| 142 | #define EC_PSW_LAN (1 << 3) |
| 143 | #define EC_PSW_RTC (1 << 4) |
| 144 | #define EC_PSW_USB (1 << 5) |
| 145 | |
| 146 | #define EC_WAKE_EVEN_TID 0x84 |
| 147 | #define EC_WID_IKB (1 << 0) |
| 148 | #define EC_WID_TP (1 << 1) |
| 149 | #define EC_WID_LID (1 << 2) |
| 150 | #define EC_WID_PWRSW (1 << 7) |
| 151 | |
| 152 | #define EC_CODE_STATE 0x85 |
| 153 | #define EC_COS_INITIAL_STAGE 0xBB |
| 154 | #define EC_COS_EC_RO 0xC0 |
| 155 | #define EC_COS_EC_RW 0xC1 |
| 156 | |
| 157 | #define EC_FW_REASON_ID 0x86 |
| 158 | #define EC_FWR_NOT_RO 0x00 |
| 159 | #define EC_FWR_GPI_ASSERTED 0x01 |
| 160 | #define EC_FWR_HOTKEY_PRESSED 0x02 |
| 161 | #define EC_FWR_FIRMWARE_CORRUPT 0x03 |
| 162 | |
| 163 | #define EC_SHUTDOWN_REASON 0xB9 |
| 164 | #define EC_FW_VER0 0xBA |
| 165 | #define EC_FW_VER1 0xBB |
| 166 | #define EC_FW_VER2 0xBC |
| 167 | #define EC_FW_VER3 0xBD |
| 168 | #define EC_FW_VER4 0xBE |
| 169 | #define EC_FW_VER5 0xBF |
| 170 | #define EC_SMBPTCL 0xC0 |
| 171 | #define EC_SMBSTA 0xC1 |
| 172 | #define EC_SMBADDR 0xC2 |
| 173 | #define EC_SMBCMD 0xC3 |
| 174 | #define EC_SMBDATA 0xC4 |
| 175 | #define EC_SMBBCNT 0xE4 |
| 176 | |
| 177 | /***************************************************************************** |
| 178 | * SMI / SCI event status |
| 179 | */ |
| 180 | #define Q_EVENT_LID_STATUS 0x06 |
| 181 | #define Q_EVENT_WIFI_BUTTON 0x06 |
| 182 | #define Q_EVENT_THERM_EVENT 0x08 |
| 183 | #define Q_EVENT_PSTATE_DOWN 0x0E |
| 184 | #define Q_EVENT_PSTATE_UP 0x0F |
| 185 | #define Q_EVENT_AC_PLUGGED 0x10 |
| 186 | #define Q_EVENT_AC_UNPLUGGED 0x11 |
| 187 | #define Q_EVENT_BATTERY_PLUGGED 0x12 |
| 188 | #define Q_EVENT_BATTERY_UNPLUGGED 0x13 |
| 189 | #define Q_EVENT_BATTERY_STATUS 0x14 |
| 190 | |
| 191 | /***************************************************************************** |
| 192 | * EC Commands |
| 193 | */ |
| 194 | #define EC_CMD_ENABLE_ACPI_MODE 0x71 |
| 195 | #define EC_CMD_DISABLE_ACPI_MODE 0x72 |
| 196 | #define EC_CMD_DISABLE_SMBUS_EVENT 0x73 |
| 197 | #define EC_CMD_ENABLE_SMBUS_EVENT 0x74 |
| 198 | #define EC_CMD_SYSTEM_RESET 0x78 |
| 199 | #define EC_CMD_SYSTEM_SHUTDOWN 0x79 |
| 200 | #define EC_CMD_RESET_FOR_FW_UPDATE 0x7D |
| 201 | #define EC_CMD_IDLE_FOR SPI_UPDATE 0x7E |
| 202 | #define EC_CMD_READ_RAM 0x80 |
| 203 | #define EC_CMD_WRITE_RAM 0x81 |
| 204 | #define EC_CMD_BURST_ENABLE 0x82 |
| 205 | #define EC_CMD_BURST_DISABLE 0x83 |
| 206 | #define EC_CMD_QUERY_EVENT 0x84 |
| 207 | |
| 208 | |
| 209 | #endif /* _EC_QUANTA_ENE_KB3940Q_EC_H */ |