Timothy Pearson | c522fc8 | 2015-02-02 18:25:34 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Timothy Pearson | c522fc8 | 2015-02-02 18:25:34 -0600 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | /* Portions marked below taken from XGI/SiS Linux kernel drivers */ |
| 18 | |
| 19 | #ifndef _XGI_COREBOOT_ |
| 20 | #define _XGI_COREBOOT_ |
| 21 | |
| 22 | #include <delay.h> |
| 23 | #include <stdlib.h> |
| 24 | #include <stdint.h> |
| 25 | #include <string.h> |
| 26 | #include <arch/io.h> |
| 27 | |
| 28 | #include <console/console.h> |
| 29 | #include <device/device.h> |
| 30 | #include <device/pci.h> |
| 31 | #include <device/pci_ids.h> |
| 32 | #include <device/pci_ops.h> |
| 33 | |
| 34 | #include "initdef.h" |
| 35 | |
| 36 | /* Begin code taken from Linux kernel 3.18.5 */ |
| 37 | |
| 38 | /* For 315/Xabre series */ |
| 39 | #define COMMAND_QUEUE_AREA_SIZE (512 * 1024) /* 512K */ |
| 40 | #define COMMAND_QUEUE_AREA_SIZE_Z7 (128 * 1024) /* 128k for XGI Z7 */ |
| 41 | #define HW_CURSOR_AREA_SIZE_315 16384 /* 16K */ |
| 42 | #define COMMAND_QUEUE_THRESHOLD 0x1F |
| 43 | |
| 44 | #define SIS_OH_ALLOC_SIZE 4000 |
| 45 | #define SENTINEL 0x7fffffff |
| 46 | |
| 47 | #define SEQ_ADR 0x14 |
| 48 | #define SEQ_DATA 0x15 |
| 49 | #define DAC_ADR 0x18 |
| 50 | #define DAC_DATA 0x19 |
| 51 | #define CRTC_ADR 0x24 |
| 52 | #define CRTC_DATA 0x25 |
| 53 | #define DAC2_ADR (0x16-0x30) |
| 54 | #define DAC2_DATA (0x17-0x30) |
| 55 | #define VB_PART1_ADR (0x04-0x30) |
| 56 | #define VB_PART1_DATA (0x05-0x30) |
| 57 | #define VB_PART2_ADR (0x10-0x30) |
| 58 | #define VB_PART2_DATA (0x11-0x30) |
| 59 | #define VB_PART3_ADR (0x12-0x30) |
| 60 | #define VB_PART3_DATA (0x13-0x30) |
| 61 | #define VB_PART4_ADR (0x14-0x30) |
| 62 | #define VB_PART4_DATA (0x15-0x30) |
| 63 | |
| 64 | #define SISSR ivideo->SiS_Pr.SiS_P3c4 |
| 65 | #define SISCR ivideo->SiS_Pr.SiS_P3d4 |
| 66 | #define SISDACA ivideo->SiS_Pr.SiS_P3c8 |
| 67 | #define SISDACD ivideo->SiS_Pr.SiS_P3c9 |
| 68 | #define SISPART1 ivideo->SiS_Pr.SiS_Part1Port |
| 69 | #define SISPART2 ivideo->SiS_Pr.SiS_Part2Port |
| 70 | #define SISPART3 ivideo->SiS_Pr.SiS_Part3Port |
| 71 | #define SISPART4 ivideo->SiS_Pr.SiS_Part4Port |
| 72 | #define SISPART5 ivideo->SiS_Pr.SiS_Part5Port |
| 73 | #define SISDAC2A SISPART5 |
| 74 | #define SISDAC2D (SISPART5 + 1) |
| 75 | #define SISMISCR (ivideo->SiS_Pr.RelIO + 0x1c) |
| 76 | #define SISMISCW ivideo->SiS_Pr.SiS_P3c2 |
| 77 | #define SISINPSTAT (ivideo->SiS_Pr.RelIO + 0x2a) |
| 78 | #define SISPEL ivideo->SiS_Pr.SiS_P3c6 |
| 79 | #define SISVGAENABLE (ivideo->SiS_Pr.RelIO + 0x13) |
| 80 | #define SISVID (ivideo->SiS_Pr.RelIO + 0x02 - 0x30) |
| 81 | #define SISCAP (ivideo->SiS_Pr.RelIO + 0x00 - 0x30) |
| 82 | |
| 83 | #define IND_SIS_PASSWORD 0x05 /* SRs */ |
| 84 | #define IND_SIS_COLOR_MODE 0x06 |
| 85 | #define IND_SIS_RAMDAC_CONTROL 0x07 |
| 86 | #define IND_SIS_DRAM_SIZE 0x14 |
| 87 | #define IND_SIS_MODULE_ENABLE 0x1E |
| 88 | #define IND_SIS_PCI_ADDRESS_SET 0x20 |
| 89 | #define IND_SIS_TURBOQUEUE_ADR 0x26 |
| 90 | #define IND_SIS_TURBOQUEUE_SET 0x27 |
| 91 | #define IND_SIS_POWER_ON_TRAP 0x38 |
| 92 | #define IND_SIS_POWER_ON_TRAP2 0x39 |
| 93 | #define IND_SIS_CMDQUEUE_SET 0x26 |
| 94 | #define IND_SIS_CMDQUEUE_THRESHOLD 0x27 |
| 95 | |
| 96 | #define IND_SIS_AGP_IO_PAD 0x48 |
| 97 | |
| 98 | #define SIS_CRT2_WENABLE_300 0x24 /* Part1 */ |
| 99 | #define SIS_CRT2_WENABLE_315 0x2F |
| 100 | |
| 101 | #define SIS_PASSWORD 0x86 /* SR05 */ |
| 102 | |
| 103 | #define SIS_INTERLACED_MODE 0x20 /* SR06 */ |
| 104 | #define SIS_8BPP_COLOR_MODE 0x0 |
| 105 | #define SIS_15BPP_COLOR_MODE 0x1 |
| 106 | #define SIS_16BPP_COLOR_MODE 0x2 |
| 107 | #define SIS_32BPP_COLOR_MODE 0x4 |
| 108 | |
| 109 | #define SIS_ENABLE_2D 0x40 /* SR1E */ |
| 110 | |
| 111 | #define SIS_MEM_MAP_IO_ENABLE 0x01 /* SR20 */ |
| 112 | #define SIS_PCI_ADDR_ENABLE 0x80 |
| 113 | |
| 114 | #define SIS_AGP_CMDQUEUE_ENABLE 0x80 /* 315/330/340 series SR26 */ |
| 115 | #define SIS_VRAM_CMDQUEUE_ENABLE 0x40 |
| 116 | #define SIS_MMIO_CMD_ENABLE 0x20 |
| 117 | #define SIS_CMD_QUEUE_SIZE_512k 0x00 |
| 118 | #define SIS_CMD_QUEUE_SIZE_1M 0x04 |
| 119 | #define SIS_CMD_QUEUE_SIZE_2M 0x08 |
| 120 | #define SIS_CMD_QUEUE_SIZE_4M 0x0C |
| 121 | #define SIS_CMD_QUEUE_RESET 0x01 |
| 122 | #define SIS_CMD_AUTO_CORR 0x02 |
| 123 | |
| 124 | #define SIS_CMD_QUEUE_SIZE_Z7_64k 0x00 /* XGI Z7 */ |
| 125 | #define SIS_CMD_QUEUE_SIZE_Z7_128k 0x04 |
| 126 | |
| 127 | #define SIS_SIMULTANEOUS_VIEW_ENABLE 0x01 /* CR30 */ |
| 128 | #define SIS_MODE_SELECT_CRT2 0x02 |
| 129 | #define SIS_VB_OUTPUT_COMPOSITE 0x04 |
| 130 | #define SIS_VB_OUTPUT_SVIDEO 0x08 |
| 131 | #define SIS_VB_OUTPUT_SCART 0x10 |
| 132 | #define SIS_VB_OUTPUT_LCD 0x20 |
| 133 | #define SIS_VB_OUTPUT_CRT2 0x40 |
| 134 | #define SIS_VB_OUTPUT_HIVISION 0x80 |
| 135 | |
| 136 | #define SIS_VB_OUTPUT_DISABLE 0x20 /* CR31 */ |
| 137 | #define SIS_DRIVER_MODE 0x40 |
| 138 | |
| 139 | #define SIS_VB_COMPOSITE 0x01 /* CR32 */ |
| 140 | #define SIS_VB_SVIDEO 0x02 |
| 141 | #define SIS_VB_SCART 0x04 |
| 142 | #define SIS_VB_LCD 0x08 |
| 143 | #define SIS_VB_CRT2 0x10 |
| 144 | #define SIS_CRT1 0x20 |
| 145 | #define SIS_VB_HIVISION 0x40 |
| 146 | #define SIS_VB_YPBPR 0x80 |
| 147 | #define SIS_VB_TV (SIS_VB_COMPOSITE | SIS_VB_SVIDEO | \ |
| 148 | SIS_VB_SCART | SIS_VB_HIVISION | SIS_VB_YPBPR) |
| 149 | |
| 150 | #define SIS_EXTERNAL_CHIP_MASK 0x0E /* CR37 (< SiS 660) */ |
| 151 | #define SIS_EXTERNAL_CHIP_SIS301 0x01 /* in CR37 << 1 ! */ |
| 152 | #define SIS_EXTERNAL_CHIP_LVDS 0x02 |
| 153 | #define SIS_EXTERNAL_CHIP_TRUMPION 0x03 |
| 154 | #define SIS_EXTERNAL_CHIP_LVDS_CHRONTEL 0x04 |
| 155 | #define SIS_EXTERNAL_CHIP_CHRONTEL 0x05 |
| 156 | #define SIS310_EXTERNAL_CHIP_LVDS 0x02 |
| 157 | #define SIS310_EXTERNAL_CHIP_LVDS_CHRONTEL 0x03 |
| 158 | |
| 159 | #define SIS_AGP_2X 0x20 /* CR48 */ |
| 160 | |
| 161 | /* vbflags, private entries (others in sisfb.h) */ |
| 162 | #define VB_CONEXANT 0x00000800 /* 661 series only */ |
| 163 | #define VB_TRUMPION VB_CONEXANT /* 300 series only */ |
| 164 | #define VB_302ELV 0x00004000 |
| 165 | #define VB_301 0x00100000 /* Video bridge type */ |
| 166 | #define VB_301B 0x00200000 |
| 167 | #define VB_302B 0x00400000 |
| 168 | #define VB_30xBDH 0x00800000 /* 30xB DH version (w/o LCD support) */ |
| 169 | #define VB_LVDS 0x01000000 |
| 170 | #define VB_CHRONTEL 0x02000000 |
| 171 | #define VB_301LV 0x04000000 |
| 172 | #define VB_302LV 0x08000000 |
| 173 | #define VB_301C 0x10000000 |
| 174 | |
| 175 | #define VB_SISBRIDGE (VB_301|VB_301B|VB_301C|VB_302B|VB_301LV|VB_302LV|VB_302ELV) |
| 176 | #define VB_VIDEOBRIDGE (VB_SISBRIDGE | VB_LVDS | VB_CHRONTEL | VB_CONEXANT) |
| 177 | |
| 178 | enum _SIS_LCD_TYPE { |
| 179 | LCD_INVALID = 0, |
| 180 | LCD_800x600, |
| 181 | LCD_1024x768, |
| 182 | LCD_1280x1024, |
| 183 | LCD_1280x960, |
| 184 | LCD_640x480, |
| 185 | LCD_1600x1200, |
| 186 | LCD_1920x1440, |
| 187 | LCD_2048x1536, |
| 188 | LCD_320x240, /* FSTN */ |
| 189 | LCD_1400x1050, |
| 190 | LCD_1152x864, |
| 191 | LCD_1152x768, |
| 192 | LCD_1280x768, |
| 193 | LCD_1024x600, |
| 194 | LCD_320x240_2, /* DSTN */ |
| 195 | LCD_320x240_3, /* DSTN */ |
| 196 | LCD_848x480, |
| 197 | LCD_1280x800, |
| 198 | LCD_1680x1050, |
| 199 | LCD_1280x720, |
| 200 | LCD_1280x854, |
| 201 | LCD_CUSTOM, |
| 202 | LCD_UNKNOWN |
| 203 | }; |
| 204 | |
| 205 | /* End code taken from Linux kernel 3.18.5 */ |
| 206 | |
Timothy Pearson | 08c15ed | 2015-02-05 01:02:57 -0600 | [diff] [blame] | 207 | #define DEFAULT_TEXT_MODE 16 /* index for 800x600x8 */ |
| 208 | |
Timothy Pearson | c522fc8 | 2015-02-02 18:25:34 -0600 | [diff] [blame] | 209 | /* coreboot <--> kernel code interface */ |
| 210 | #define __iomem |
| 211 | #define SISIOMEMTYPE |
| 212 | typedef unsigned long SISIOADDRESS; |
| 213 | typedef u64 phys_addr_t; |
| 214 | #define pci_dev device |
| 215 | |
| 216 | #define SZ_16M 0x01000000 |
| 217 | |
| 218 | #define min_t(type, x, y) ({ \ |
| 219 | type __min1 = (x); \ |
| 220 | type __min2 = (y); \ |
| 221 | __min1 < __min2 ? __min1 : __min2; }) |
| 222 | |
| 223 | #define dev_info(dev, format, arg...) printk(BIOS_INFO, "XGI VGA: " format, ##arg) |
| 224 | #define dev_dbg(dev, format, arg...) printk(BIOS_DEBUG, "XGI VGA: " format, ##arg) |
| 225 | #define dev_err(dev, format, arg...) printk(BIOS_ERR, "XGI VGA: " format, ##arg) |
| 226 | |
| 227 | #define pr_info(format, arg...) printk(BIOS_INFO, "XGI VGA: " format, ##arg) |
| 228 | #define pr_debug(format, arg...) printk(BIOS_INFO, "XGI VGA: " format, ##arg) |
| 229 | #define pr_err(format, arg...) printk(BIOS_ERR, "XGI VGA: " format, ##arg) |
| 230 | |
| 231 | static inline void writel(u32 val, volatile void *addr) { |
| 232 | *(u32*)addr = val; |
| 233 | } |
| 234 | |
| 235 | static inline u32 readl(const volatile void *addr) { |
| 236 | return *(u32*)addr; |
| 237 | } |
| 238 | |
| 239 | static inline int pci_read_config_dword(struct pci_dev *dev, int where, |
| 240 | u32 *val) |
| 241 | { |
| 242 | *val = pci_read_config32(dev, where); |
| 243 | return 0; |
| 244 | } |
| 245 | |
| 246 | static inline int pci_read_config_byte(struct pci_dev *dev, int where, |
| 247 | u8 *val) |
| 248 | { |
| 249 | *val = pci_read_config8(dev, where); |
| 250 | return 0; |
| 251 | } |
| 252 | |
| 253 | static inline struct resource* resource_at_bar(struct pci_dev *dev, u8 bar) { |
| 254 | struct resource *res = dev->resource_list; |
| 255 | int i; |
| 256 | for (i = 0; i < bar; i++) { |
| 257 | res = res->next; |
| 258 | if (res == NULL) |
| 259 | return NULL; |
| 260 | } |
| 261 | |
| 262 | return res; |
| 263 | } |
| 264 | |
| 265 | static inline resource_t pci_resource_len(struct pci_dev *dev, u8 bar) { |
| 266 | struct resource *res = resource_at_bar(dev, bar); |
| 267 | if (res) |
| 268 | return res->size; |
| 269 | else |
| 270 | return 0; |
| 271 | } |
| 272 | |
| 273 | static inline resource_t pci_resource_start(struct pci_dev *dev, u8 bar) { |
| 274 | struct resource *res = resource_at_bar(dev, bar); |
| 275 | if (res) |
| 276 | return res->base; |
| 277 | else |
| 278 | return 0; |
| 279 | } |
| 280 | |
| 281 | struct xgifb_video_info *pci_get_drvdata(struct pci_dev *pdev); |
| 282 | void pci_set_drvdata(struct pci_dev *pdev, struct xgifb_video_info *data); |
| 283 | |
| 284 | int xgifb_probe(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info); |
| 285 | int xgifb_modeset(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info); |
| 286 | |
| 287 | #endif |