Stefan Reinauer | 85b0fa1 | 2010-12-17 00:08:21 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2003 Eric Biederman |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 85b0fa1 | 2010-12-17 00:08:21 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
Kyösti Mälkki | bea6bf0 | 2014-01-30 15:45:16 +0200 | [diff] [blame] | 16 | #ifndef UART8250REG_H |
| 17 | #define UART8250REG_H |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 18 | |
Stefan Reinauer | 85b0fa1 | 2010-12-17 00:08:21 +0000 | [diff] [blame] | 19 | /* Data */ |
Gabe Black | 77ffa0d | 2013-09-30 21:25:49 -0700 | [diff] [blame] | 20 | #define UART8250_RBR 0x00 |
| 21 | #define UART8250_TBR 0x00 |
Stefan Reinauer | 85b0fa1 | 2010-12-17 00:08:21 +0000 | [diff] [blame] | 22 | |
| 23 | /* Control */ |
Gabe Black | 77ffa0d | 2013-09-30 21:25:49 -0700 | [diff] [blame] | 24 | #define UART8250_IER 0x01 |
| 25 | #define UART8250_IER_MSI 0x08 /* Enable Modem status interrupt */ |
| 26 | #define UART8250_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
| 27 | #define UART8250_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
| 28 | #define UART8250_IER_RDI 0x01 /* Enable receiver data interrupt */ |
Stefan Reinauer | 85b0fa1 | 2010-12-17 00:08:21 +0000 | [diff] [blame] | 29 | |
Gabe Black | 77ffa0d | 2013-09-30 21:25:49 -0700 | [diff] [blame] | 30 | #define UART8250_IIR 0x02 |
| 31 | #define UART8250_IIR_NO_INT 0x01 /* No interrupts pending */ |
| 32 | #define UART8250_IIR_ID 0x06 /* Mask for the interrupt ID */ |
Stefan Reinauer | 85b0fa1 | 2010-12-17 00:08:21 +0000 | [diff] [blame] | 33 | |
Gabe Black | 77ffa0d | 2013-09-30 21:25:49 -0700 | [diff] [blame] | 34 | #define UART8250_IIR_MSI 0x00 /* Modem status interrupt */ |
| 35 | #define UART8250_IIR_THRI 0x02 /* Transmitter holding register empty */ |
| 36 | #define UART8250_IIR_RDI 0x04 /* Receiver data interrupt */ |
| 37 | #define UART8250_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
Stefan Reinauer | 85b0fa1 | 2010-12-17 00:08:21 +0000 | [diff] [blame] | 38 | |
Gabe Black | 77ffa0d | 2013-09-30 21:25:49 -0700 | [diff] [blame] | 39 | #define UART8250_FCR 0x02 |
| 40 | #define UART8250_FCR_FIFO_EN 0x01 /* Fifo enable */ |
| 41 | #define UART8250_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ |
| 42 | #define UART8250_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ |
| 43 | #define UART8250_FCR_DMA_SELECT 0x08 /* For DMA applications */ |
| 44 | #define UART8250_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ |
| 45 | #define UART8250_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ |
| 46 | #define UART8250_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ |
| 47 | #define UART8250_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ |
| 48 | #define UART8250_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ |
Stefan Reinauer | 85b0fa1 | 2010-12-17 00:08:21 +0000 | [diff] [blame] | 49 | |
Gabe Black | 77ffa0d | 2013-09-30 21:25:49 -0700 | [diff] [blame] | 50 | #define UART8250_FCR_RXSR 0x02 /* Receiver soft reset */ |
| 51 | #define UART8250_FCR_TXSR 0x04 /* Transmitter soft reset */ |
Stefan Reinauer | 85b0fa1 | 2010-12-17 00:08:21 +0000 | [diff] [blame] | 52 | |
Gabe Black | 77ffa0d | 2013-09-30 21:25:49 -0700 | [diff] [blame] | 53 | #define UART8250_LCR 0x03 |
| 54 | #define UART8250_LCR_WLS_MSK 0x03 /* character length select mask */ |
| 55 | #define UART8250_LCR_WLS_5 0x00 /* 5 bit character length */ |
| 56 | #define UART8250_LCR_WLS_6 0x01 /* 6 bit character length */ |
| 57 | #define UART8250_LCR_WLS_7 0x02 /* 7 bit character length */ |
| 58 | #define UART8250_LCR_WLS_8 0x03 /* 8 bit character length */ |
| 59 | #define UART8250_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ |
| 60 | #define UART8250_LCR_PEN 0x08 /* Parity enable */ |
| 61 | #define UART8250_LCR_EPS 0x10 /* Even Parity Select */ |
| 62 | #define UART8250_LCR_STKP 0x20 /* Stick Parity */ |
| 63 | #define UART8250_LCR_SBRK 0x40 /* Set Break */ |
| 64 | #define UART8250_LCR_BKSE 0x80 /* Bank select enable */ |
| 65 | #define UART8250_LCR_DLAB 0x80 /* Divisor latch access bit */ |
Stefan Reinauer | 85b0fa1 | 2010-12-17 00:08:21 +0000 | [diff] [blame] | 66 | |
Gabe Black | 77ffa0d | 2013-09-30 21:25:49 -0700 | [diff] [blame] | 67 | #define UART8250_MCR 0x04 |
| 68 | #define UART8250_MCR_DTR 0x01 /* DTR */ |
| 69 | #define UART8250_MCR_RTS 0x02 /* RTS */ |
| 70 | #define UART8250_MCR_OUT1 0x04 /* Out 1 */ |
| 71 | #define UART8250_MCR_OUT2 0x08 /* Out 2 */ |
| 72 | #define UART8250_MCR_LOOP 0x10 /* Enable loopback test mode */ |
Stefan Reinauer | 85b0fa1 | 2010-12-17 00:08:21 +0000 | [diff] [blame] | 73 | |
Gabe Black | 77ffa0d | 2013-09-30 21:25:49 -0700 | [diff] [blame] | 74 | #define UART8250_MCR_DMA_EN 0x04 |
| 75 | #define UART8250_MCR_TX_DFR 0x08 |
Stefan Reinauer | 85b0fa1 | 2010-12-17 00:08:21 +0000 | [diff] [blame] | 76 | |
Gabe Black | 77ffa0d | 2013-09-30 21:25:49 -0700 | [diff] [blame] | 77 | #define UART8250_DLL 0x00 |
| 78 | #define UART8250_DLM 0x01 |
Stefan Reinauer | 85b0fa1 | 2010-12-17 00:08:21 +0000 | [diff] [blame] | 79 | |
| 80 | /* Status */ |
Gabe Black | 77ffa0d | 2013-09-30 21:25:49 -0700 | [diff] [blame] | 81 | #define UART8250_LSR 0x05 |
| 82 | #define UART8250_LSR_DR 0x01 /* Data ready */ |
| 83 | #define UART8250_LSR_OE 0x02 /* Overrun */ |
| 84 | #define UART8250_LSR_PE 0x04 /* Parity error */ |
| 85 | #define UART8250_LSR_FE 0x08 /* Framing error */ |
| 86 | #define UART8250_LSR_BI 0x10 /* Break */ |
| 87 | #define UART8250_LSR_THRE 0x20 /* Xmit holding register empty */ |
| 88 | #define UART8250_LSR_TEMT 0x40 /* Xmitter empty */ |
| 89 | #define UART8250_LSR_ERR 0x80 /* Error */ |
Stefan Reinauer | 85b0fa1 | 2010-12-17 00:08:21 +0000 | [diff] [blame] | 90 | |
Gabe Black | 77ffa0d | 2013-09-30 21:25:49 -0700 | [diff] [blame] | 91 | #define UART8250_MSR 0x06 |
| 92 | #define UART8250_MSR_DCD 0x80 /* Data Carrier Detect */ |
| 93 | #define UART8250_MSR_RI 0x40 /* Ring Indicator */ |
| 94 | #define UART8250_MSR_DSR 0x20 /* Data Set Ready */ |
| 95 | #define UART8250_MSR_CTS 0x10 /* Clear to Send */ |
| 96 | #define UART8250_MSR_DDCD 0x08 /* Delta DCD */ |
| 97 | #define UART8250_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
| 98 | #define UART8250_MSR_DDSR 0x02 /* Delta DSR */ |
| 99 | #define UART8250_MSR_DCTS 0x01 /* Delta CTS */ |
Stefan Reinauer | 85b0fa1 | 2010-12-17 00:08:21 +0000 | [diff] [blame] | 100 | |
Gabe Black | 77ffa0d | 2013-09-30 21:25:49 -0700 | [diff] [blame] | 101 | #define UART8250_SCR 0x07 |
| 102 | #define UART8250_SPR 0x07 |
Stefan Reinauer | 85b0fa1 | 2010-12-17 00:08:21 +0000 | [diff] [blame] | 103 | |
Kyösti Mälkki | bea6bf0 | 2014-01-30 15:45:16 +0200 | [diff] [blame] | 104 | #endif /* UART8250REG_H */ |