David Hendricks | 90a42d8 | 2013-06-14 16:06:11 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Samsung Electronics |
| 3 | * Rajeshwari Shinde <rajeshwari.s@samsung.com> |
| 4 | * |
David Hendricks | 90a42d8 | 2013-06-14 16:06:11 -0700 | [diff] [blame] | 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License as |
| 7 | * published by the Free Software Foundation; either version 2 of |
| 8 | * the License, or (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
David Hendricks | 90a42d8 | 2013-06-14 16:06:11 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #ifndef __MAX77802_H_ |
| 17 | #define __MAX77802_H_ |
| 18 | |
| 19 | enum { |
| 20 | MAX77802_REG_PMIC_ID = 0x0, |
| 21 | MAX77802_REG_PMIC_INTSRC, |
| 22 | MAX77802_REG_PMIC_INT1, |
| 23 | MAX77802_REG_PMIC_INT2, |
| 24 | MAX77802_REG_PMIC_INT1MSK, |
| 25 | MAX77802_REG_PMIC_INT2MSK, |
| 26 | |
| 27 | MAX77802_REG_PMIC_STATUS1, |
| 28 | MAX77802_REG_PMIC_STATUS2, |
| 29 | |
| 30 | MAX77802_REG_PMIC_PWRON, |
| 31 | MAX77802_REG_PMIC_MRSTB = 0xA, |
| 32 | MAX77802_REG_PMIC_EPWRHOLD, |
| 33 | MAX77802_REG_PMIC_BOOSTCTRL = 0xE, |
| 34 | MAX77802_REG_PMIC_BOOSTOUT, |
| 35 | |
| 36 | MAX77802_REG_PMIC_BUCK1CTRL = 0x10, |
| 37 | MAX77802_REG_PMIC_BUCK1DVS1, |
| 38 | MAX77802_REG_PMIC_BUCK1DVS2, |
| 39 | MAX77802_REG_PMIC_BUCK1DVS3, |
| 40 | MAX77802_REG_PMIC_BUCK1DVS4, |
| 41 | MAX77802_REG_PMIC_BUCK1DVS5, |
| 42 | MAX77802_REG_PMIC_BUCK1DVS6, |
| 43 | MAX77802_REG_PMIC_BUCK1DVS7, |
| 44 | MAX77802_REG_PMIC_BUCK1DVS8, |
| 45 | |
| 46 | MAX77802_REG_PMIC_BUCK234FREQ, |
| 47 | MAX77802_REG_PMIC_BUCK2CTRL1, |
| 48 | MAX77802_REG_PMIC_BUCK2CTRL2, |
| 49 | MAX77802_REG_PMIC_BUCK2PHTRAN, |
| 50 | |
| 51 | MAX77802_REG_PMIC_BUCK2DVS1, |
| 52 | MAX77802_REG_PMIC_BUCK2DVS2, |
| 53 | MAX77802_REG_PMIC_BUCK2DVS3, |
| 54 | MAX77802_REG_PMIC_BUCK2DVS4, |
| 55 | MAX77802_REG_PMIC_BUCK2DVS5, |
| 56 | MAX77802_REG_PMIC_BUCK2DVS6, |
| 57 | MAX77802_REG_PMIC_BUCK2DVS7, |
| 58 | MAX77802_REG_PMIC_BUCK2DVS8, |
| 59 | MAX77802_REG_PMIC_BUCK3CTRL1 = 0x27, |
| 60 | MAX77802_REG_PMIC_BUCK3DVS1, |
| 61 | MAX77802_REG_PMIC_BUCK3DVS2, |
| 62 | MAX77802_REG_PMIC_BUCK3DVS3, |
| 63 | MAX77802_REG_PMIC_BUCK3DVS4, |
| 64 | MAX77802_REG_PMIC_BUCK3DVS5, |
| 65 | MAX77802_REG_PMIC_BUCK3DVS6, |
| 66 | MAX77802_REG_PMIC_BUCK3DVS7, |
| 67 | MAX77802_REG_PMIC_BUCK3DVS8, |
| 68 | MAX77802_REG_PMIC_BUCK4CTRL1 = 0x37, |
| 69 | MAX77802_REG_PMIC_BUCK4DVS1, |
| 70 | MAX77802_REG_PMIC_BUCK4DVS2, |
| 71 | MAX77802_REG_PMIC_BUCK4DVS3, |
| 72 | MAX77802_REG_PMIC_BUCK4DVS4, |
| 73 | MAX77802_REG_PMIC_BUCK4DVS5, |
| 74 | MAX77802_REG_PMIC_BUCK4DVS6, |
| 75 | MAX77802_REG_PMIC_BUCK4DVS7, |
| 76 | MAX77802_REG_PMIC_BUCK4DVS8, |
| 77 | MAX77802_REG_PMIC_BUCK5CTRL1 = 0x40, |
| 78 | MAX77802_REG_PMIC_BUCK5CTRL, |
| 79 | MAX77802_REG_PMIC_BUCK5OUT, |
| 80 | |
| 81 | MAX77802_REG_PMIC_BUCK6CTRL = 0x44, |
| 82 | MAX77802_REG_PMIC_BUCK6DVS1, |
| 83 | MAX77802_REG_PMIC_BUCK6DVS2, |
| 84 | MAX77802_REG_PMIC_BUCK6DVS3, |
| 85 | MAX77802_REG_PMIC_BUCK6DVS4, |
| 86 | MAX77802_REG_PMIC_BUCK6DVS5, |
| 87 | MAX77802_REG_PMIC_BUCK6DVS6, |
| 88 | MAX77802_REG_PMIC_BUCK6DVS7, |
| 89 | MAX77802_REG_PMIC_BUCK6DVS8, |
| 90 | |
| 91 | MAX77802_REG_PMIC_BUCK7CTRL = 0x4E, |
| 92 | MAX77802_REG_PMIC_BUCK7OUT, |
| 93 | |
| 94 | MAX77802_REG_PMIC_BUCK8CTRL = 0x51, |
| 95 | MAX77802_REG_PMIC_BUCK8OUT, |
| 96 | |
| 97 | MAX77802_REG_PMIC_BUCK9CTRL = 0x54, |
| 98 | MAX77802_REG_PMIC_BUCK9OUT, |
| 99 | |
| 100 | MAX77802_REG_PMIC_BUCK10CTRL = 0x57, |
| 101 | MAX77802_REG_PMIC_BUCK10OUT, |
| 102 | |
| 103 | MAX77802_REG_PMIC_LDO1CTRL1 = 0x60, |
| 104 | MAX77802_REG_PMIC_LDO2CTRL1, |
| 105 | MAX77802_REG_PMIC_LDO3CTRL1, |
| 106 | MAX77802_REG_PMIC_LDO4CTRL1, |
| 107 | MAX77802_REG_PMIC_LDO5CTRL1, |
| 108 | MAX77802_REG_PMIC_LDO6CTRL1, |
| 109 | MAX77802_REG_PMIC_LDO7CTRL1, |
| 110 | MAX77802_REG_PMIC_LDO8CTRL1, |
| 111 | MAX77802_REG_PMIC_LDO9CTRL1, |
| 112 | MAX77802_REG_PMIC_LDO10CTRL1, |
| 113 | MAX77802_REG_PMIC_LDO11CTRL1, |
| 114 | MAX77802_REG_PMIC_LDO12CTRL1, |
| 115 | MAX77802_REG_PMIC_LDO13CTRL1, |
| 116 | MAX77802_REG_PMIC_LDO14CTRL1, |
| 117 | MAX77802_REG_PMIC_LDO15CTRL1, |
| 118 | |
| 119 | MAX77802_REG_PMIC_LDO17CTRL1 = 0x70, |
| 120 | MAX77802_REG_PMIC_LDO18CTRL1, |
| 121 | MAX77802_REG_PMIC_LDO19CTRL1, |
| 122 | MAX77802_REG_PMIC_LDO20CTRL1, |
| 123 | MAX77802_REG_PMIC_LDO21CTRL1, |
| 124 | |
| 125 | MAX77802_REG_PMIC_LDO23CTRL1 = 0x76, |
| 126 | MAX77802_REG_PMIC_LDO24CTRL1, |
| 127 | MAX77802_REG_PMIC_LDO25CTRL1, |
| 128 | MAX77802_REG_PMIC_LDO26CTRL1, |
| 129 | MAX77802_REG_PMIC_LDO27CTRL1 = 0x7A, |
| 130 | MAX77802_REG_PMIC_LDO28CTRL1, |
| 131 | MAX77802_REG_PMIC_LDO29CTRL1, |
| 132 | MAX77802_REG_PMIC_LDO30CTRL1, |
| 133 | MAX77802_REG_PMIC_LDO32CTRL1 = 0x7F, |
| 134 | MAX77802_REG_PMIC_LDO33CTRL1, |
| 135 | MAX77802_REG_PMIC_LDO34CTRL1, |
| 136 | MAX77802_REG_PMIC_LDO35CTRL1, |
| 137 | |
| 138 | MAX77802_REG_PMIC_LDO1CTRL2 = 0x90, |
| 139 | MAX77802_REG_PMIC_LDO2CTRL2, |
| 140 | MAX77802_REG_PMIC_LDO3CTRL2, |
| 141 | MAX77802_REG_PMIC_LDO4CTRL2, |
| 142 | MAX77802_REG_PMIC_LDO5CTRL2, |
| 143 | MAX77802_REG_PMIC_LDO6CTRL2 = 0x95, |
| 144 | MAX77802_REG_PMIC_LDO7CTRL2, |
| 145 | MAX77802_REG_PMIC_LDO8CTRL2, |
| 146 | MAX77802_REG_PMIC_LDO9CTRL2, |
| 147 | MAX77802_REG_PMIC_LDO10CTRL2, |
| 148 | MAX77802_REG_PMIC_LDO11CTRL2, |
| 149 | MAX77802_REG_PMIC_LDO12CTRL2, |
| 150 | MAX77802_REG_PMIC_LDO13CTRL2, |
| 151 | MAX77802_REG_PMIC_LDO14CTRL2, |
| 152 | MAX77802_REG_PMIC_LDO15CTRL2, |
| 153 | |
| 154 | MAX77802_REG_PMIC_LDO17CTRL2 = 0xA0, |
| 155 | MAX77802_REG_PMIC_LDO18CTRL2, |
| 156 | MAX77802_REG_PMIC_LDO19CTRL2, |
| 157 | MAX77802_REG_PMIC_LDO20CTRL2, |
| 158 | MAX77802_REG_PMIC_LDO21CTRL2, |
| 159 | MAX77802_REG_PMIC_LDO22CTRL2, |
| 160 | MAX77802_REG_PMIC_LDO23CTRL2, |
| 161 | MAX77802_REG_PMIC_LDO24CTRL2, |
| 162 | MAX77802_REG_PMIC_LDO25CTRL2, |
| 163 | MAX77802_REG_PMIC_LDO26CTRL2, |
| 164 | MAX77802_REG_PMIC_LDO27CTRL2 = 0xAA, |
| 165 | MAX77802_REG_PMIC_LDO28CTRL2, |
| 166 | MAX77802_REG_PMIC_LDO29CTRL2, |
| 167 | MAX77802_REG_PMIC_LDO30CTRL2, |
| 168 | MAX77802_REG_PMIC_LDO32CTRL2 = 0xAF, |
| 169 | MAX77802_REG_PMIC_LDO33CTRL2 = 0xB0, |
| 170 | MAX77802_REG_PMIC_LDO34CTRL2, |
| 171 | MAX77802_REG_PMIC_LDO35CTRL2, |
| 172 | |
| 173 | MAX77802_REG_PMIC_BBAT = 0xB4, |
| 174 | MAX77802_REG_PMIC_32KHZ, |
| 175 | |
| 176 | MAX77802_NUM_OF_REGS, |
| 177 | }; |
| 178 | |
| 179 | /* I2C device address for pmic max77686 */ |
| 180 | #define MAX77802_I2C_ADDR (0x12 >> 1) |
| 181 | |
| 182 | enum { |
| 183 | LDO_OFF = 0, |
| 184 | LDO_ON, |
| 185 | |
| 186 | DIS_LDO = (0x00 << 6), |
| 187 | EN_LDO = (0x3 << 6), |
| 188 | }; |
| 189 | |
| 190 | /* Buck1 1.0 volt value (P1.0V_AP_MIF) */ |
David Hendricks | ea3a463 | 2013-08-01 18:48:26 -0700 | [diff] [blame] | 191 | #define MAX77802_BUCK1DVS1_1V 0x3E |
David Hendricks | 90a42d8 | 2013-06-14 16:06:11 -0700 | [diff] [blame] | 192 | /* Buck2 1.0 volt value (P1.0V_VDD_ARM) */ |
David Hendricks | ea3a463 | 2013-08-01 18:48:26 -0700 | [diff] [blame] | 193 | #define MAX77802_BUCK2DVS1_1V 0x40 |
| 194 | /* Buck2 1.2625 volt value (P1.2625V_VDD_ARM) */ |
| 195 | #define MAX77802_BUCK2DVS1_1_2625V 0x6A |
David Hendricks | 90a42d8 | 2013-06-14 16:06:11 -0700 | [diff] [blame] | 196 | /* Buck3 1.0 volt value (P1.0V_VDD_INT) */ |
David Hendricks | ea3a463 | 2013-08-01 18:48:26 -0700 | [diff] [blame] | 197 | #define MAX77802_BUCK3DVS1_1V 0x40 |
David Hendricks | 90a42d8 | 2013-06-14 16:06:11 -0700 | [diff] [blame] | 198 | /* Buck4 1.0 volt value (P1.0V_VDD_G3D) */ |
David Hendricks | ea3a463 | 2013-08-01 18:48:26 -0700 | [diff] [blame] | 199 | #define MAX77802_BUCK4DVS1_1V 0x40 |
David Hendricks | 90a42d8 | 2013-06-14 16:06:11 -0700 | [diff] [blame] | 200 | /* Buck6 1.0 volt value (P1.0V_AP_KFC) */ |
David Hendricks | ea3a463 | 2013-08-01 18:48:26 -0700 | [diff] [blame] | 201 | #define MAX77802_BUCK6DVS1_1V 0x3E |
David Hendricks | 90a42d8 | 2013-06-14 16:06:11 -0700 | [diff] [blame] | 202 | |
| 203 | /* |
| 204 | * Different Bucks use different bits to control power. There are two types, |
| 205 | * defined below. |
| 206 | */ |
| 207 | /* Type 1, works for BUCKs 1, 5, 6...10 */ |
| 208 | #define MAX77802_BUCK_TYPE1_ON (1 << 0) |
| 209 | #define MAX77802_BUCK_TYPE1_IGNORE_PWRREQ (1 << 1) |
| 210 | |
| 211 | /* Type 2, works for BUCKs 2...4 */ |
| 212 | #define MAX77802_BUCK_TYPE2_ON (1 << 4) |
| 213 | #define MAX77802_BUCK_TYPE2_IGNORE_PWRREQ (1 << 5) |
| 214 | |
| 215 | /* LDO35 1.2 volt value for bridge ic */ |
| 216 | #define MAX77802_LDO35CTRL1_1_2V (1 << 4) |
| 217 | #define MAX77802_LOD35CTRL1_ON (1 << 6) |
| 218 | |
David Hendricks | ea3a463 | 2013-08-01 18:48:26 -0700 | [diff] [blame] | 219 | /* Disable Boost Mode*/ |
| 220 | #define MAX77802_BOOSTCTRL_OFF 0x09 |
| 221 | |
David Hendricks | 90a42d8 | 2013-06-14 16:06:11 -0700 | [diff] [blame] | 222 | /* |
| 223 | * MAX77802_REG_PMIC_32KHZ set to 32KH CP |
| 224 | * output is activated |
| 225 | */ |
| 226 | #define MAX77802_32KHCP_EN (1 << 1) |
| 227 | |
| 228 | /* |
| 229 | * MAX77802_REG_PMIC_BBAT set to |
| 230 | * Back up batery charger on and |
| 231 | * limit voltage setting to 3.5v |
| 232 | */ |
| 233 | #define MAX77802_BBCHOSTEN (1 << 0) |
| 234 | #define MAX77802_BBCVS_3_5V (3 << 3) |
| 235 | |
| 236 | #endif /* __MAX77802_H_ */ |