blob: afcec91d4cefb2d1235feab80a7c721d15953aaa [file] [log] [blame]
Ronald G. Minnich74fade42013-10-01 10:46:35 -07001/*
2 * Copyright 2013 Google Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28/* This code was created by the coccinnelle filters in the i915tool,
29 * with some final hand filtering.
30 */
31
32#include <console/console.h>
33#include <stdint.h>
34#include <delay.h>
35#include <drivers/intel/gma/i915.h>
36#include <string.h>
37
38void compute_display_params(struct intel_dp *dp)
39{
40 struct edid *edid = &(dp->edid);
David Hendricks7dbf9c62015-07-30 18:49:48 -070041 struct edid_mode *mode = &edid->mode;
Ronald G. Minnich74fade42013-10-01 10:46:35 -070042
43 /* step 1: get the constants in the dp struct set up. */
44 dp->lane_count = dp->dpcd[DP_MAX_LANE_COUNT]&DP_LANE_COUNT_MASK;
45
46 dp->link_bw = dp->dpcd[DP_MAX_LINK_RATE];
47 dp->clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
48 dp->edid.link_clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
49
50 /* step 2. Do some computation of other stuff. */
51 dp->bytes_per_pixel = dp->pipe_bits_per_pixel/8;
52
53 dp->stride = edid->bytes_per_line;
54
David Hendricks7dbf9c62015-07-30 18:49:48 -070055 dp->htotal = (mode->ha - 1) | ((mode->ha + mode->hbl - 1) << 16);
Ronald G. Minnich74fade42013-10-01 10:46:35 -070056
David Hendricks7dbf9c62015-07-30 18:49:48 -070057 dp->hblank = (mode->ha - 1) | ((mode->ha + mode->hbl - 1) << 16);
Ronald G. Minnich74fade42013-10-01 10:46:35 -070058
David Hendricks7dbf9c62015-07-30 18:49:48 -070059 dp->hsync = (mode->ha + mode->hso - 1) |
60 ((mode->ha + mode->hso + mode->hspw - 1) << 16);
Ronald G. Minnich74fade42013-10-01 10:46:35 -070061
David Hendricks7dbf9c62015-07-30 18:49:48 -070062 dp->vtotal = (mode->va - 1) | ((mode->va + mode->vbl - 1) << 16);
Ronald G. Minnich74fade42013-10-01 10:46:35 -070063
David Hendricks7dbf9c62015-07-30 18:49:48 -070064 dp->vblank = (mode->va - 1) | ((mode->va + mode->vbl - 1) << 16);
Ronald G. Minnich74fade42013-10-01 10:46:35 -070065
David Hendricks7dbf9c62015-07-30 18:49:48 -070066 dp->vsync = (mode->va + mode->vso - 1) |
67 ((mode->va + mode->vso + mode->vspw - 1) << 16);
Ronald G. Minnich74fade42013-10-01 10:46:35 -070068
69 /* PIPEASRC is wid-1 x ht-1 */
David Hendricks7dbf9c62015-07-30 18:49:48 -070070 dp->pipesrc = (mode->ha-1)<<16 | (mode->va-1);
Ronald G. Minnich74fade42013-10-01 10:46:35 -070071
72 dp->pfa_pos = 0;
73
74 dp->pfa_ctl = PF_ENABLE | PF_FILTER_MED_3x3;
75 /* IVB hack */
76 if (dp->gen == 6)
77 dp->pfa_ctl |= PF_PIPE_SEL_IVB(dp->pipe);
78
David Hendricks7dbf9c62015-07-30 18:49:48 -070079 dp->pfa_sz = (mode->ha << 16) | (mode->va);
Ronald G. Minnich74fade42013-10-01 10:46:35 -070080
81 /* step 3. Call the linux code we pulled in. */
82 dp->flags = intel_ddi_calc_transcoder_flags(edid->panel_bits_per_pixel,
83 dp->port,
84 dp->pipe,
85 dp->type,
86 dp->lane_count,
87 dp->pfa_sz,
David Hendricks7dbf9c62015-07-30 18:49:48 -070088 mode->phsync == '+'?1:0,
89 mode->pvsync == '+'?1:0);
Ronald G. Minnich74fade42013-10-01 10:46:35 -070090
91 dp->transcoder = intel_ddi_get_transcoder(dp->port,
92 dp->pipe);
93
94 intel_dp_compute_m_n(edid->panel_bits_per_pixel,
95 dp->lane_count,
David Hendricks7dbf9c62015-07-30 18:49:48 -070096 dp->edid.mode.pixel_clock,
Ronald G. Minnich74fade42013-10-01 10:46:35 -070097 dp->edid.link_clock,
98 &dp->m_n);
99
100 printk(BIOS_SPEW, "dp->lane_count = 0x%08x\n",dp->lane_count);
101 printk(BIOS_SPEW, "dp->stride = 0x%08x\n",dp->stride);
102 printk(BIOS_SPEW, "dp->htotal = 0x%08x\n", dp->htotal);
103 printk(BIOS_SPEW, "dp->hblank = 0x%08x\n", dp->hblank);
104 printk(BIOS_SPEW, "dp->hsync = 0x%08x\n", dp->hsync);
105 printk(BIOS_SPEW, "dp->vtotal = 0x%08x\n", dp->vtotal);
106 printk(BIOS_SPEW, "dp->vblank = 0x%08x\n", dp->vblank);
107 printk(BIOS_SPEW, "dp->vsync = 0x%08x\n", dp->vsync);
108 printk(BIOS_SPEW, "dp->pipesrc = 0x%08x\n", dp->pipesrc);
109 printk(BIOS_SPEW, "dp->pfa_pos = 0x%08x\n", dp->pfa_pos);
110 printk(BIOS_SPEW, "dp->pfa_ctl = 0x%08x\n", dp->pfa_ctl);
111 printk(BIOS_SPEW, "dp->pfa_sz = 0x%08x\n", dp->pfa_sz);
112 printk(BIOS_SPEW, "dp->link_m = 0x%08x\n", dp->m_n.link_m);
113 printk(BIOS_SPEW, "dp->link_n = 0x%08x\n", dp->m_n.link_n);
114 printk(BIOS_SPEW, "0x6f030 = 0x%08x\n",
115 TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m);
116 printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", dp->m_n.gmch_m);
117 printk(BIOS_SPEW, "0x6f034 = 0x%08x\n", dp->m_n.gmch_n);
118 printk(BIOS_SPEW, "dp->flags = 0x%08x\n", dp->flags);
119}