Timothy Pearson | 04cf449 | 2015-09-05 17:38:09 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Red Hat Inc. |
| 3 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the |
| 7 | * "Software"), to deal in the Software without restriction, including |
| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
| 10 | * permit persons to whom the Software is furnished to do so, subject to |
| 11 | * the following conditions: |
| 12 | * |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 20 | * |
| 21 | * The above copyright notice and this permission notice (including the |
| 22 | * next paragraph) shall be included in all copies or substantial portions |
| 23 | * of the Software. |
| 24 | * |
| 25 | */ |
| 26 | /* |
| 27 | * Authors: Dave Airlie <airlied@redhat.com> |
| 28 | */ |
| 29 | #ifndef __AST_DRV_H__ |
| 30 | #define __AST_DRV_H__ |
| 31 | |
| 32 | #include "aspeed_coreboot.h" |
| 33 | |
| 34 | #define PCI_CHIP_AST2000 0x2000 |
| 35 | #define PCI_CHIP_AST2100 0x2010 |
| 36 | #define PCI_CHIP_AST1180 0x1180 |
| 37 | |
| 38 | |
| 39 | enum ast_chip { |
| 40 | AST2000, |
| 41 | AST2100, |
| 42 | AST1100, |
| 43 | AST2200, |
| 44 | AST2150, |
| 45 | AST2300, |
| 46 | AST2400, |
| 47 | AST1180, |
| 48 | }; |
| 49 | |
| 50 | enum ast_tx_chip { |
| 51 | AST_TX_NONE, |
| 52 | AST_TX_SIL164, |
| 53 | AST_TX_ITE66121, |
| 54 | AST_TX_DP501, |
| 55 | }; |
| 56 | |
| 57 | #define AST_DRAM_512Mx16 0 |
| 58 | #define AST_DRAM_1Gx16 1 |
| 59 | #define AST_DRAM_512Mx32 2 |
| 60 | #define AST_DRAM_1Gx32 3 |
| 61 | #define AST_DRAM_2Gx16 6 |
| 62 | #define AST_DRAM_4Gx16 7 |
| 63 | |
| 64 | struct ast_fbdev; |
| 65 | |
| 66 | struct ast_private { |
| 67 | struct drm_device *dev; |
| 68 | |
| 69 | void __iomem *regs; |
| 70 | void __iomem *ioregs; |
| 71 | bool io_space_uses_mmap; |
| 72 | |
| 73 | enum ast_chip chip; |
| 74 | bool vga2_clone; |
| 75 | uint32_t dram_bus_width; |
| 76 | uint32_t dram_type; |
| 77 | uint32_t mclk; |
| 78 | uint32_t vram_size; |
| 79 | |
| 80 | struct ast_fbdev *fbdev; |
| 81 | |
| 82 | int fb_mtrr; |
| 83 | |
| 84 | struct drm_gem_object *cursor_cache; |
| 85 | uint64_t cursor_cache_gpu_addr; |
| 86 | |
| 87 | int next_cursor; |
| 88 | bool support_wide_screen; |
| 89 | |
| 90 | enum ast_tx_chip tx_chip_type; |
| 91 | u8 dp501_maxclk; |
| 92 | u8 *dp501_fw_addr; |
| 93 | const struct firmware *dp501_fw; /* dp501 fw */ |
| 94 | }; |
| 95 | |
| 96 | int ast_driver_load(struct drm_device *dev, unsigned long flags); |
| 97 | int ast_driver_unload(struct drm_device *dev); |
| 98 | |
| 99 | #define AST_IO_AR_PORT_WRITE (0x40) |
| 100 | #define AST_IO_MISC_PORT_WRITE (0x42) |
| 101 | #define AST_IO_VGA_ENABLE_PORT (0x43) |
| 102 | #define AST_IO_SEQ_PORT (0x44) |
| 103 | #define AST_IO_DAC_INDEX_READ (0x47) |
| 104 | #define AST_IO_DAC_INDEX_WRITE (0x48) |
| 105 | #define AST_IO_DAC_DATA (0x49) |
| 106 | #define AST_IO_GR_PORT (0x4E) |
| 107 | #define AST_IO_CRTC_PORT (0x54) |
| 108 | #define AST_IO_INPUT_STATUS1_READ (0x5A) |
| 109 | #define AST_IO_MISC_PORT_READ (0x4C) |
| 110 | |
| 111 | #define AST_IO_MM_OFFSET (0x380) |
| 112 | |
| 113 | #define __ast_read(x) \ |
| 114 | static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \ |
| 115 | u##x val = 0;\ |
| 116 | val = ioread##x(ast->regs + reg); \ |
| 117 | return val;\ |
| 118 | } |
| 119 | |
| 120 | __ast_read(8); |
| 121 | __ast_read(16); |
| 122 | __ast_read(32) |
| 123 | |
| 124 | #define __ast_io_read(x) \ |
| 125 | static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \ |
| 126 | u##x val = 0;\ |
| 127 | if (ast->io_space_uses_mmap) \ |
| 128 | val = ioread##x(ast->regs + reg); \ |
| 129 | else \ |
| 130 | val = ioread_cbio##x(ast->ioregs + reg); \ |
| 131 | return val;\ |
| 132 | } |
| 133 | |
| 134 | __ast_io_read(8); |
| 135 | __ast_io_read(16); |
| 136 | __ast_io_read(32); |
| 137 | |
| 138 | #define __ast_write(x) \ |
| 139 | static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\ |
| 140 | iowrite##x(val, ast->regs + reg);\ |
| 141 | } |
| 142 | |
| 143 | __ast_write(8); |
| 144 | __ast_write(16); |
| 145 | __ast_write(32); |
| 146 | |
| 147 | #define __ast_io_write(x) \ |
| 148 | static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\ |
| 149 | if (ast->io_space_uses_mmap) \ |
| 150 | iowrite##x(val, ast->regs + reg);\ |
| 151 | else \ |
| 152 | iowrite_cbio##x(val, ast->ioregs + reg);\ |
| 153 | } |
| 154 | |
| 155 | __ast_io_write(8); |
| 156 | __ast_io_write(16); |
| 157 | #undef __ast_io_write |
| 158 | |
| 159 | static inline void ast_set_index_reg(struct ast_private *ast, |
| 160 | uint32_t base, uint8_t index, |
| 161 | uint8_t val) |
| 162 | { |
| 163 | ast_io_write16(ast, base, ((u16)val << 8) | index); |
| 164 | } |
| 165 | |
| 166 | void ast_set_index_reg_mask(struct ast_private *ast, |
| 167 | uint32_t base, uint8_t index, |
| 168 | uint8_t mask, uint8_t val); |
| 169 | uint8_t ast_get_index_reg(struct ast_private *ast, |
| 170 | uint32_t base, uint8_t index); |
| 171 | uint8_t ast_get_index_reg_mask(struct ast_private *ast, |
| 172 | uint32_t base, uint8_t index, uint8_t mask); |
| 173 | |
| 174 | static inline void ast_open_key(struct ast_private *ast) |
| 175 | { |
| 176 | ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8); |
| 177 | } |
| 178 | |
| 179 | #define AST_VIDMEM_SIZE_8M 0x00800000 |
| 180 | #define AST_VIDMEM_SIZE_16M 0x01000000 |
| 181 | #define AST_VIDMEM_SIZE_32M 0x02000000 |
| 182 | #define AST_VIDMEM_SIZE_64M 0x04000000 |
| 183 | #define AST_VIDMEM_SIZE_128M 0x08000000 |
| 184 | |
| 185 | #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M |
| 186 | |
| 187 | #define AST_MAX_HWC_WIDTH 64 |
| 188 | #define AST_MAX_HWC_HEIGHT 64 |
| 189 | |
| 190 | #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH*AST_MAX_HWC_HEIGHT*2) |
| 191 | #define AST_HWC_SIGNATURE_SIZE 32 |
| 192 | |
| 193 | #define AST_DEFAULT_HWC_NUM 2 |
| 194 | /* define for signature structure */ |
| 195 | #define AST_HWC_SIGNATURE_CHECKSUM 0x00 |
| 196 | #define AST_HWC_SIGNATURE_SizeX 0x04 |
| 197 | #define AST_HWC_SIGNATURE_SizeY 0x08 |
| 198 | #define AST_HWC_SIGNATURE_X 0x0C |
| 199 | #define AST_HWC_SIGNATURE_Y 0x10 |
| 200 | #define AST_HWC_SIGNATURE_HOTSPOTX 0x14 |
| 201 | #define AST_HWC_SIGNATURE_HOTSPOTY 0x18 |
| 202 | |
| 203 | #define AST_MM_ALIGN_SHIFT 4 |
| 204 | #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1) |
| 205 | |
| 206 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) |
| 207 | |
| 208 | /* ast post */ |
| 209 | void ast_enable_vga(struct drm_device *dev); |
| 210 | void ast_enable_mmio(struct drm_device *dev); |
| 211 | bool ast_is_vga_enabled(struct drm_device *dev); |
| 212 | void ast_post_gpu(struct drm_device *dev); |
| 213 | u32 ast_mindwm(struct ast_private *ast, u32 r); |
| 214 | void ast_moutdwm(struct ast_private *ast, u32 r, u32 v); |
| 215 | /* ast dp501 */ |
| 216 | int ast_load_dp501_microcode(struct drm_device *dev); |
| 217 | void ast_set_dp501_video_output(struct drm_device *dev, u8 mode); |
| 218 | bool ast_launch_m68k(struct drm_device *dev); |
| 219 | bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); |
| 220 | bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata); |
| 221 | u8 ast_get_dp501_max_clk(struct drm_device *dev); |
| 222 | void ast_init_3rdtx(struct drm_device *dev); |
| 223 | #endif |