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Lee Leahye1ba3da2015-03-31 17:30:01 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
5 * Copyright (C) 2015 Intel Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahye1ba3da2015-03-31 17:30:01 -070015 */
16
17#include <device/device.h>
18#include <device/pci.h>
19#include <device/pciexp.h>
20#include <device/pci_ids.h>
21#include <stdlib.h>
22
23typedef struct {
24 const unsigned char subclass_id;
25 const char *subclass_name;
26} PCI_SUBCLASS;
27
28typedef struct {
29 const unsigned char class_id;
30 const PCI_SUBCLASS *subclass_list;
31 const unsigned int subclass_entries;
32 const char *class_name;
33} PCI_CLASS;
34
35static const PCI_SUBCLASS unclassified[] = {
36 { 0x00, "Non-VGA device" },
37 { 0x01, "VGA compatible device" }
38};
39
40static const PCI_SUBCLASS mass_storage[] = {
41 { 0x00, "SCSI storage controller" },
42 { 0x01, "IDE interface" },
43 { 0x02, "Floppy disk controller" },
44 { 0x03, "IPI bus controller" },
45 { 0x04, "RAID bus controller" },
46 { 0x05, "ATA controller" },
47 { 0x06, "SATA controller" },
48 { 0x07, "Serial Attached SCSI controller" },
49 { 0x08, "Non-Volatile memory controller" },
50 { 0x80, "Mass storage controller" }
51};
52
53static const PCI_SUBCLASS network[] = {
54 { 0x00, "Ethernet controller" },
55 { 0x01, "Token ring network controller" },
56 { 0x02, "FDDI network controller" },
57 { 0x03, "ATM network controller" },
58 { 0x04, "ISDN controller" },
59 { 0x05, "WorldFip controller" },
60 { 0x06, "PICMG controller" },
61 { 0x80, "Network controller" }
62};
63
64static const PCI_SUBCLASS display[] = {
65 { 0x00, "VGA compatible controller" },
66 { 0x01, "XGA compatible controller" },
67 { 0x02, "3D controller" },
68 { 0x80, "Display controller" }
69};
70
71static const PCI_SUBCLASS multimedia[] = {
72 { 0x00, "Multimedia video controller" },
73 { 0x01, "Multimedia audio controller" },
74 { 0x02, "Computer telephony device" },
75 { 0x03, "Audio device" },
76 { 0x80, "Multimedia controller" }
77};
78
79static const PCI_SUBCLASS memory[] = {
80 { 0x00, "RAM memory" },
81 { 0x01, "FLASH memory" },
82 { 0x80, "Memory controller" }
83};
84
85static const PCI_SUBCLASS bridge[] = {
86 { 0x00, "Host bridge" },
87 { 0x01, "ISA bridge" },
88 { 0x02, "EISA bridge" },
89 { 0x03, "MicroChannel bridge" },
90 { 0x04, "PCI bridge" },
91 { 0x05, "PCMCIA bridge" },
92 { 0x06, "NuBus bridge" },
93 { 0x07, "CardBus bridge" },
94 { 0x08, "RACEway bridge" },
95 { 0x09, "Semi-transparent PCI-to-PCI bridge" },
96 { 0x0a, "InfiniBand to PCI host bridge" },
97 { 0x80, "Bridge" }
98};
99
100static const PCI_SUBCLASS communication[] = {
101 { 0x00, "Serial controller" },
102 { 0x01, "Parallel controller" },
103 { 0x02, "Multiport serial controller" },
104 { 0x03, "Modem" },
105 { 0x04, "GPIB controller" },
106 { 0x05, "Smard Card controller" },
107 { 0x80, "Communication controller" }
108};
109
110static const PCI_SUBCLASS generic[] = {
111 { 0x00, "PIC" },
112 { 0x01, "DMA controller" },
113 { 0x02, "Timer" },
114 { 0x03, "RTC" },
115 { 0x04, "PCI Hot-plug controller" },
116 { 0x05, "SD Host controller" },
117 { 0x06, "IOMMU" },
118 { 0x80, "System peripheral" }
119};
120
121static const PCI_SUBCLASS input_device[] = {
122 { 0x00, "Keyboard controller" },
123 { 0x01, "Digitizer Pen" },
124 { 0x02, "Mouse controller" },
125 { 0x03, "Scanner controller" },
126 { 0x04, "Gameport controller" },
127 { 0x80, "Input device controller" }
128};
129
130static const PCI_SUBCLASS docking_station[] = {
131 { 0x00, "Generic Docking Station" },
132 { 0x80, "Docking Station" }
133};
134
135static const PCI_SUBCLASS processor[] = {
136 { 0x00, "386" },
137 { 0x01, "486" },
138 { 0x02, "Pentium" },
139 { 0x10, "Alpha" },
140 { 0x20, "Power PC" },
141 { 0x30, "MIPS" },
142 { 0x40, "Co-processor" }
143};
144
145static const PCI_SUBCLASS serial_bus[] = {
146 { 0x00, "FireWire (IEEE 1394)" },
147 { 0x01, "ACCESS Bus" },
148 { 0x02, "SSA" },
149 { 0x03, "USB controller" },
150 { 0x04, "Fibre Channel" },
151 { 0x05, "SMBus" },
152 { 0x06, "InfiniBand" },
153 { 0x07, "IPMI SMIC interface" },
154 { 0x08, "SERCOS interface" },
155 { 0x09, "CANBUS" }
156};
157
158static const PCI_SUBCLASS wireless[] = {
159 { 0x00, "IRDA controller" },
160 { 0x01, "Consumer IR controller" },
161 { 0x10, "RF controller" },
162 { 0x11, "Bluetooth" },
163 { 0x12, "Broadband" },
164 { 0x20, "802.1a controller" },
165 { 0x21, "802.1b controller" },
166 { 0x80, "Wireless controller" }
167};
168
169static const PCI_SUBCLASS intellegient_controller[] = {
170 { 0x00, "I2O" }
171};
172
173static const PCI_SUBCLASS satellite_controller[] = {
174 { 0x01, "Satellite TV controller" },
175 { 0x02, "Satellite audio communication controller" },
176 { 0x03, "Satellite voice communication controller" },
177 { 0x04, "Satellite data communication controller" }
178};
179
180static const PCI_SUBCLASS encryption[] = {
181 { 0x00, "Network and computing encryption device" },
182 { 0x10, "Entertainment encryption device" },
183 { 0x80, "Encryption controller" }
184};
185
186static const PCI_SUBCLASS signal_processing[] = {
187 { 0x00, "DPIO module" },
188 { 0x01, "Performance counters" },
189 { 0x10, "Communication synchronizer" },
190 { 0x20, "Signal processing management" },
191 { 0x80, "Signal processing controller" }
192};
193
194static const PCI_CLASS class_list[] = {
195 { 0x00, &unclassified[0], ARRAY_SIZE(unclassified),
196 "Unclassified device" },
197 { 0x01, &mass_storage[0], ARRAY_SIZE(mass_storage), "Mass storage" },
198 { 0x02, &network[0], ARRAY_SIZE(network), "Network" },
199 { 0x03, &display[0], ARRAY_SIZE(display), "Display" },
200 { 0x04, &multimedia[0], ARRAY_SIZE(multimedia), "Multimedia" },
201 { 0x05, &memory[0], ARRAY_SIZE(memory), "Memory" },
202 { 0x06, &bridge[0], ARRAY_SIZE(bridge), "Bridge" },
203 { 0x07, &communication[0], ARRAY_SIZE(communication), "Communication" },
204 { 0x08, &generic[0], ARRAY_SIZE(generic), "Generic system peripheral" },
205 { 0x09, &input_device[0], ARRAY_SIZE(input_device), "Input device" },
206 { 0x0a, &docking_station[0], ARRAY_SIZE(docking_station),
207 "Docking station" },
208 { 0x0b, &processor[0], ARRAY_SIZE(processor), "Processor" },
209 { 0x0c, &serial_bus[0], ARRAY_SIZE(serial_bus), "Serial bus" },
210 { 0x0d, &wireless[0], ARRAY_SIZE(wireless), "Wireless" },
211 { 0x0e, &intellegient_controller[0],
212 ARRAY_SIZE(intellegient_controller),
213 "Intelligent controller" },
214 { 0x0f, &satellite_controller[0], ARRAY_SIZE(satellite_controller),
215 "Satellite communications" },
216 { 0x10, &encryption[0], ARRAY_SIZE(encryption), "Encryption" },
217 { 0x11, &signal_processing[0], ARRAY_SIZE(signal_processing),
218 "Signal processing" },
219 { 0xff, NULL, 0, "Unassigned class" }
220};
221static const unsigned int class_entries = ARRAY_SIZE(class_list);
222
223static const PCI_CLASS *get_pci_class_entry(device_t dev)
224{
225 unsigned char class;
226 const PCI_CLASS *class_entry;
227 const PCI_CLASS *class_list_end;
228
229 /* Get the PCI device class */
230 class = pci_read_config8(dev, PCI_CLASS_DEVICE+1);
231
232 /* Locate the class entry */
233 class_entry = &class_list[0];
234 class_list_end = &class_entry[class_entries];
235 while (class_list_end > class_entry) {
236 if (class_entry->class_id == class)
237 return class_entry;
238 class_entry += 1;
239 }
240 return NULL;
241}
242
243const char *get_pci_class_name(device_t dev)
244{
245 const PCI_CLASS *class_entry;
246
247 class_entry = get_pci_class_entry(dev);
248 return class_entry ? class_entry->class_name : "???";
249}
250
251const char *get_pci_subclass_name(device_t dev)
252{
253 const PCI_CLASS *class_entry;
254 unsigned char subclass;
255 const PCI_SUBCLASS *subclass_entry;
256 const PCI_SUBCLASS *subclass_list_end;
257 const char *subclass_name;
258
259 /* Get the PCI device subclass */
260 subclass = pci_read_config8(dev, PCI_CLASS_DEVICE);
261
262 /* Locate the subclass name */
263 subclass_name = "???";
264 class_entry = get_pci_class_entry(dev);
265 subclass_entry = class_entry ? class_entry->subclass_list : NULL;
266 if (NULL != subclass_entry) {
267 subclass_list_end =
268 &subclass_entry[class_entry->subclass_entries];
269 while (subclass_list_end > subclass_entry) {
270 if (subclass_entry->subclass_id == subclass) {
271 subclass_name = subclass_entry->subclass_name;
272 break;
273 }
274 subclass_entry += 1;
275 }
276 }
277 return subclass_name;
278}