Yinghai Lu | 72ee9b0 | 2005-12-14 02:39:33 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 1bfbbc0 | 2012-06-07 14:00:07 -0700 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2001 Eric Biederman |
| 5 | * Copyright (C) 2001 Ronald G. Minnich |
| 6 | * Copyright (C) 2005 Yinghai Lu |
| 7 | * Copyright (C) 2008 coresystems GmbH |
Timothy Pearson | 6b6c653 | 2015-09-05 19:31:20 -0500 | [diff] [blame] | 8 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
Stefan Reinauer | 1bfbbc0 | 2012-06-07 14:00:07 -0700 | [diff] [blame] | 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
Stefan Reinauer | 1bfbbc0 | 2012-06-07 14:00:07 -0700 | [diff] [blame] | 18 | */ |
Yinghai Lu | 72ee9b0 | 2005-12-14 02:39:33 +0000 | [diff] [blame] | 19 | |
Aaron Durbin | 029aaf6 | 2013-10-10 12:41:49 -0500 | [diff] [blame] | 20 | #include <cpu/x86/cr.h> |
Kyösti Mälkki | bae775a | 2014-12-18 10:36:33 +0200 | [diff] [blame] | 21 | #include <cpu/x86/gdt.h> |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 22 | #include <cpu/x86/lapic.h> |
| 23 | #include <delay.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 24 | #include <halt.h> |
Stefan Reinauer | 75dbc38 | 2012-10-15 15:19:43 -0700 | [diff] [blame] | 25 | #include <lib.h> |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 26 | #include <string.h> |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 27 | #include <symbols.h> |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 28 | #include <console/console.h> |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 29 | #include <device/device.h> |
| 30 | #include <device/path.h> |
| 31 | #include <smp/atomic.h> |
| 32 | #include <smp/spinlock.h> |
| 33 | #include <cpu/cpu.h> |
Stefan Reinauer | 2bdfb48 | 2012-04-03 16:17:11 -0700 | [diff] [blame] | 34 | #include <cpu/intel/speedstep.h> |
Aaron Durbin | 38c326d | 2013-05-06 12:22:23 -0500 | [diff] [blame] | 35 | #include <thread.h> |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 36 | |
Ronald G. Minnich | 000bf83c | 2012-06-06 13:00:24 -0700 | [diff] [blame] | 37 | #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 38 | /* This is a lot more paranoid now, since Linux can NOT handle |
Zheng Bao | d4c5c44 | 2010-02-20 09:38:16 +0000 | [diff] [blame] | 39 | * being told there is a CPU when none exists. So any errors |
| 40 | * will return 0, meaning no CPU. |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 41 | * |
| 42 | * We actually handling that case by noting which cpus startup |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 43 | * and not telling anyone about the ones that don't. |
Zheng Bao | d4c5c44 | 2010-02-20 09:38:16 +0000 | [diff] [blame] | 44 | */ |
Kyösti Mälkki | 63539bb | 2012-07-05 06:31:15 +0300 | [diff] [blame] | 45 | |
| 46 | /* Start-UP IPI vector must be 4kB aligned and below 1MB. */ |
| 47 | #define AP_SIPI_VECTOR 0x1000 |
Yinghai Lu | 72ee9b0 | 2005-12-14 02:39:33 +0000 | [diff] [blame] | 48 | |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 49 | #if CONFIG_HAVE_ACPI_RESUME |
Rudolf Marek | a572f83 | 2009-04-13 17:57:44 +0000 | [diff] [blame] | 50 | char *lowmem_backup; |
| 51 | char *lowmem_backup_ptr; |
| 52 | int lowmem_backup_size; |
| 53 | #endif |
| 54 | |
Aaron Durbin | a146d58 | 2013-02-08 16:56:51 -0600 | [diff] [blame] | 55 | static inline void setup_secondary_gdt(void) |
| 56 | { |
| 57 | u16 *gdt_limit; |
Stefan Reinauer | e021dea | 2015-06-18 01:15:27 -0700 | [diff] [blame] | 58 | #ifdef __x86_64__ |
| 59 | u64 *gdt_base; |
| 60 | #else |
Aaron Durbin | a146d58 | 2013-02-08 16:56:51 -0600 | [diff] [blame] | 61 | u32 *gdt_base; |
Stefan Reinauer | e021dea | 2015-06-18 01:15:27 -0700 | [diff] [blame] | 62 | #endif |
Aaron Durbin | a146d58 | 2013-02-08 16:56:51 -0600 | [diff] [blame] | 63 | |
| 64 | gdt_limit = (void *)&_secondary_gdt_addr; |
| 65 | gdt_base = (void *)&gdt_limit[1]; |
| 66 | |
Stefan Reinauer | e021dea | 2015-06-18 01:15:27 -0700 | [diff] [blame] | 67 | *gdt_limit = (uintptr_t)&gdt_end - (uintptr_t)&gdt - 1; |
| 68 | *gdt_base = (uintptr_t)&gdt; |
Aaron Durbin | a146d58 | 2013-02-08 16:56:51 -0600 | [diff] [blame] | 69 | } |
Myles Watson | 6e23576 | 2009-09-29 14:56:15 +0000 | [diff] [blame] | 70 | |
Stefan Reinauer | 1bfbbc0 | 2012-06-07 14:00:07 -0700 | [diff] [blame] | 71 | static void copy_secondary_start_to_lowest_1M(void) |
Yinghai Lu | 72ee9b0 | 2005-12-14 02:39:33 +0000 | [diff] [blame] | 72 | { |
Zheng Bao | d4c5c44 | 2010-02-20 09:38:16 +0000 | [diff] [blame] | 73 | unsigned long code_size; |
Yinghai Lu | 72ee9b0 | 2005-12-14 02:39:33 +0000 | [diff] [blame] | 74 | |
Aaron Durbin | a146d58 | 2013-02-08 16:56:51 -0600 | [diff] [blame] | 75 | /* Fill in secondary_start's local gdt. */ |
| 76 | setup_secondary_gdt(); |
| 77 | |
Zheng Bao | d4c5c44 | 2010-02-20 09:38:16 +0000 | [diff] [blame] | 78 | code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start; |
Yinghai Lu | 72ee9b0 | 2005-12-14 02:39:33 +0000 | [diff] [blame] | 79 | |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 80 | #if CONFIG_HAVE_ACPI_RESUME |
Rudolf Marek | a572f83 | 2009-04-13 17:57:44 +0000 | [diff] [blame] | 81 | /* need to save it for RAM resume */ |
| 82 | lowmem_backup_size = code_size; |
| 83 | lowmem_backup = malloc(code_size); |
Kyösti Mälkki | 63539bb | 2012-07-05 06:31:15 +0300 | [diff] [blame] | 84 | lowmem_backup_ptr = (char *)AP_SIPI_VECTOR; |
Zheng Bao | d4c5c44 | 2010-02-20 09:38:16 +0000 | [diff] [blame] | 85 | |
Rudolf Marek | a572f83 | 2009-04-13 17:57:44 +0000 | [diff] [blame] | 86 | if (lowmem_backup == NULL) |
| 87 | die("Out of backup memory\n"); |
| 88 | |
Zheng Bao | d4c5c44 | 2010-02-20 09:38:16 +0000 | [diff] [blame] | 89 | memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size); |
Rudolf Marek | a572f83 | 2009-04-13 17:57:44 +0000 | [diff] [blame] | 90 | #endif |
Zheng Bao | d4c5c44 | 2010-02-20 09:38:16 +0000 | [diff] [blame] | 91 | /* copy the _secondary_start to the ram below 1M*/ |
Kyösti Mälkki | 63539bb | 2012-07-05 06:31:15 +0300 | [diff] [blame] | 92 | memcpy((unsigned char *)AP_SIPI_VECTOR, (unsigned char *)_secondary_start, code_size); |
Yinghai Lu | 72ee9b0 | 2005-12-14 02:39:33 +0000 | [diff] [blame] | 93 | |
Stefan Reinauer | 1bfbbc0 | 2012-06-07 14:00:07 -0700 | [diff] [blame] | 94 | printk(BIOS_DEBUG, "start_eip=0x%08lx, code_size=0x%08lx\n", |
| 95 | (long unsigned int)AP_SIPI_VECTOR, code_size); |
Yinghai Lu | 72ee9b0 | 2005-12-14 02:39:33 +0000 | [diff] [blame] | 96 | } |
| 97 | |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 98 | static int lapic_start_cpu(unsigned long apicid) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 99 | { |
| 100 | int timeout; |
Kyösti Mälkki | 63539bb | 2012-07-05 06:31:15 +0300 | [diff] [blame] | 101 | unsigned long send_status, accept_status; |
Ronald G. Minnich | b5e777c | 2013-07-22 20:17:18 +0200 | [diff] [blame] | 102 | int j, maxlvt; |
Zheng Bao | d4c5c44 | 2010-02-20 09:38:16 +0000 | [diff] [blame] | 103 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 104 | /* |
| 105 | * Starting actual IPI sequence... |
| 106 | */ |
| 107 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 108 | printk(BIOS_SPEW, "Asserting INIT.\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 109 | |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 110 | /* |
| 111 | * Turn INIT on target chip |
| 112 | */ |
| 113 | lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 114 | |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 115 | /* |
| 116 | * Send IPI |
| 117 | */ |
| 118 | |
| 119 | lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT |
| 120 | | LAPIC_DM_INIT); |
| 121 | |
| 122 | printk(BIOS_SPEW, "Waiting for send to finish...\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 123 | timeout = 0; |
| 124 | do { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 125 | printk(BIOS_SPEW, "+"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 126 | udelay(100); |
| 127 | send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; |
| 128 | } while (send_status && (timeout++ < 1000)); |
| 129 | if (timeout >= 1000) { |
Stefan Reinauer | 1bfbbc0 | 2012-06-07 14:00:07 -0700 | [diff] [blame] | 130 | printk(BIOS_ERR, "CPU %ld: First APIC write timed out. " |
| 131 | "Disabling\n", apicid); |
Zheng Bao | d4c5c44 | 2010-02-20 09:38:16 +0000 | [diff] [blame] | 132 | // too bad. |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 133 | printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 134 | if (lapic_read(LAPIC_ESR)) { |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 135 | printk(BIOS_ERR, "Try to reset ESR\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 136 | lapic_write_around(LAPIC_ESR, 0); |
Stefan Reinauer | 1bfbbc0 | 2012-06-07 14:00:07 -0700 | [diff] [blame] | 137 | printk(BIOS_ERR, "ESR is 0x%lx\n", |
| 138 | lapic_read(LAPIC_ESR)); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 139 | } |
| 140 | return 0; |
| 141 | } |
Vladimir Serbinenko | 533ad10 | 2013-11-14 19:23:30 +0100 | [diff] [blame] | 142 | #if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_INTEL_MODEL_206AX && !CONFIG_CPU_INTEL_MODEL_2065X |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 143 | mdelay(10); |
| 144 | #endif |
Yinghai Lu | 9a791df | 2006-04-03 20:38:34 +0000 | [diff] [blame] | 145 | |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 146 | printk(BIOS_SPEW, "Deasserting INIT.\n"); |
Sven Schnelle | 042c146 | 2012-06-17 10:32:55 +0200 | [diff] [blame] | 147 | |
| 148 | /* Target chip */ |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 149 | lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); |
Sven Schnelle | 042c146 | 2012-06-17 10:32:55 +0200 | [diff] [blame] | 150 | |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 151 | /* Send IPI */ |
| 152 | lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); |
Sven Schnelle | 042c146 | 2012-06-17 10:32:55 +0200 | [diff] [blame] | 153 | |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 154 | printk(BIOS_SPEW, "Waiting for send to finish...\n"); |
Sven Schnelle | 042c146 | 2012-06-17 10:32:55 +0200 | [diff] [blame] | 155 | timeout = 0; |
| 156 | do { |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 157 | printk(BIOS_SPEW, "+"); |
Sven Schnelle | 042c146 | 2012-06-17 10:32:55 +0200 | [diff] [blame] | 158 | udelay(100); |
| 159 | send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; |
| 160 | } while (send_status && (timeout++ < 1000)); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 161 | if (timeout >= 1000) { |
Stefan Reinauer | 1bfbbc0 | 2012-06-07 14:00:07 -0700 | [diff] [blame] | 162 | printk(BIOS_ERR, "CPU %ld: Second apic write timed out. " |
| 163 | "Disabling\n", apicid); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 164 | // too bad. |
| 165 | return 0; |
| 166 | } |
| 167 | |
Sven Schnelle | 042c146 | 2012-06-17 10:32:55 +0200 | [diff] [blame] | 168 | /* |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 169 | * Run STARTUP IPI loop. |
Sven Schnelle | 042c146 | 2012-06-17 10:32:55 +0200 | [diff] [blame] | 170 | */ |
Ronald G. Minnich | b5e777c | 2013-07-22 20:17:18 +0200 | [diff] [blame] | 171 | printk(BIOS_SPEW, "#startup loops: %d.\n", CONFIG_NUM_IPI_STARTS); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 172 | |
| 173 | maxlvt = 4; |
| 174 | |
Ronald G. Minnich | b5e777c | 2013-07-22 20:17:18 +0200 | [diff] [blame] | 175 | for (j = 1; j <= CONFIG_NUM_IPI_STARTS; j++) { |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 176 | printk(BIOS_SPEW, "Sending STARTUP #%d to %lu.\n", j, apicid); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 177 | lapic_read_around(LAPIC_SPIV); |
| 178 | lapic_write(LAPIC_ESR, 0); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 179 | lapic_read(LAPIC_ESR); |
| 180 | printk(BIOS_SPEW, "After apic_write.\n"); |
Sven Schnelle | 042c146 | 2012-06-17 10:32:55 +0200 | [diff] [blame] | 181 | |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 182 | /* |
| 183 | * STARTUP IPI |
| 184 | */ |
| 185 | |
| 186 | /* Target chip */ |
| 187 | lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); |
| 188 | |
| 189 | /* Boot on the stack */ |
| 190 | /* Kick the second */ |
| 191 | lapic_write_around(LAPIC_ICR, LAPIC_DM_STARTUP |
| 192 | | (AP_SIPI_VECTOR >> 12)); |
| 193 | |
| 194 | /* |
| 195 | * Give the other CPU some time to accept the IPI. |
| 196 | */ |
| 197 | udelay(300); |
| 198 | |
| 199 | printk(BIOS_SPEW, "Startup point 1.\n"); |
| 200 | |
| 201 | printk(BIOS_SPEW, "Waiting for send to finish...\n"); |
| 202 | timeout = 0; |
| 203 | do { |
| 204 | printk(BIOS_SPEW, "+"); |
| 205 | udelay(100); |
| 206 | send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; |
| 207 | } while (send_status && (timeout++ < 1000)); |
| 208 | |
| 209 | /* |
| 210 | * Give the other CPU some time to accept the IPI. |
| 211 | */ |
| 212 | udelay(200); |
| 213 | /* |
| 214 | * Due to the Pentium erratum 3AP. |
| 215 | */ |
| 216 | if (maxlvt > 3) { |
| 217 | lapic_read_around(LAPIC_SPIV); |
| 218 | lapic_write(LAPIC_ESR, 0); |
| 219 | } |
| 220 | accept_status = (lapic_read(LAPIC_ESR) & 0xEF); |
| 221 | if (send_status || accept_status) |
| 222 | break; |
| 223 | } |
| 224 | printk(BIOS_SPEW, "After Startup.\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 225 | if (send_status) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 226 | printk(BIOS_WARNING, "APIC never delivered???\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 227 | if (accept_status) |
Stefan Reinauer | 1bfbbc0 | 2012-06-07 14:00:07 -0700 | [diff] [blame] | 228 | printk(BIOS_WARNING, "APIC delivery error (%lx).\n", |
| 229 | accept_status); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 230 | if (send_status || accept_status) |
| 231 | return 0; |
| 232 | return 1; |
| 233 | } |
| 234 | |
Stefan Reinauer | f8ee180 | 2008-01-18 15:08:58 +0000 | [diff] [blame] | 235 | /* Number of cpus that are currently running in coreboot */ |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 236 | static atomic_t active_cpus = ATOMIC_INIT(1); |
| 237 | |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 238 | /* start_cpu_lock covers last_cpu_index and secondary_stack. |
| 239 | * Only starting one cpu at a time let's me remove the logic |
| 240 | * for select the stack from assembly language. |
| 241 | * |
| 242 | * In addition communicating by variables to the cpu I |
Ronald G. Minnich | 8b93059 | 2012-06-05 14:41:27 -0700 | [diff] [blame] | 243 | * am starting allows me to verify it has started before |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 244 | * start_cpu returns. |
| 245 | */ |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 246 | |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 247 | static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED; |
Ronald G. Minnich | 8b93059 | 2012-06-05 14:41:27 -0700 | [diff] [blame] | 248 | static unsigned int last_cpu_index = 0; |
Stefan Reinauer | 1bfbbc0 | 2012-06-07 14:00:07 -0700 | [diff] [blame] | 249 | static void *stacks[CONFIG_MAX_CPUS]; |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 250 | volatile unsigned long secondary_stack; |
Ronald G. Minnich | 8b93059 | 2012-06-05 14:41:27 -0700 | [diff] [blame] | 251 | volatile unsigned int secondary_cpu_index; |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 252 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 253 | int start_cpu(struct device *cpu) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 254 | { |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 255 | struct cpu_info *info; |
| 256 | unsigned long stack_end; |
Ronald G. Minnich | 000bf83c | 2012-06-06 13:00:24 -0700 | [diff] [blame] | 257 | unsigned long stack_base; |
| 258 | unsigned long *stack; |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 259 | unsigned long apicid; |
Ronald G. Minnich | 8b93059 | 2012-06-05 14:41:27 -0700 | [diff] [blame] | 260 | unsigned int index; |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 261 | unsigned long count; |
Ronald G. Minnich | 000bf83c | 2012-06-06 13:00:24 -0700 | [diff] [blame] | 262 | int i; |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 263 | int result; |
| 264 | |
| 265 | spin_lock(&start_cpu_lock); |
| 266 | |
Stefan Reinauer | 1bfbbc0 | 2012-06-07 14:00:07 -0700 | [diff] [blame] | 267 | /* Get the CPU's apicid */ |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 268 | apicid = cpu->path.apic.apic_id; |
| 269 | |
| 270 | /* Get an index for the new processor */ |
| 271 | index = ++last_cpu_index; |
| 272 | |
Stefan Reinauer | 1bfbbc0 | 2012-06-07 14:00:07 -0700 | [diff] [blame] | 273 | /* Find end of the new processor's stack */ |
| 274 | stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - |
| 275 | sizeof(struct cpu_info); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 276 | |
Ronald G. Minnich | 000bf83c | 2012-06-06 13:00:24 -0700 | [diff] [blame] | 277 | stack_base = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*(index+1)); |
Ronald G. Minnich | 8b93059 | 2012-06-05 14:41:27 -0700 | [diff] [blame] | 278 | printk(BIOS_SPEW, "CPU%d: stack_base %p, stack_end %p\n", index, |
Ronald G. Minnich | 000bf83c | 2012-06-06 13:00:24 -0700 | [diff] [blame] | 279 | (void *)stack_base, (void *)stack_end); |
| 280 | /* poison the stack */ |
| 281 | for(stack = (void *)stack_base, i = 0; i < CONFIG_STACK_SIZE; i++) |
| 282 | stack[i/sizeof(*stack)] = 0xDEADBEEF; |
| 283 | stacks[index] = stack; |
Stefan Reinauer | 1bfbbc0 | 2012-06-07 14:00:07 -0700 | [diff] [blame] | 284 | /* Record the index and which CPU structure we are using */ |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 285 | info = (struct cpu_info *)stack_end; |
| 286 | info->index = index; |
| 287 | info->cpu = cpu; |
Aaron Durbin | 38c326d | 2013-05-06 12:22:23 -0500 | [diff] [blame] | 288 | thread_init_cpu_info_non_bsp(info); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 289 | |
Ronald G. Minnich | 8b93059 | 2012-06-05 14:41:27 -0700 | [diff] [blame] | 290 | /* Advertise the new stack and index to start_cpu */ |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 291 | secondary_stack = stack_end; |
Ronald G. Minnich | 8b93059 | 2012-06-05 14:41:27 -0700 | [diff] [blame] | 292 | secondary_cpu_index = index; |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 293 | |
Stefan Reinauer | 1bfbbc0 | 2012-06-07 14:00:07 -0700 | [diff] [blame] | 294 | /* Until the CPU starts up report the CPU is not enabled */ |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 295 | cpu->enabled = 0; |
| 296 | cpu->initialized = 0; |
| 297 | |
| 298 | /* Start the cpu */ |
| 299 | result = lapic_start_cpu(apicid); |
| 300 | |
| 301 | if (result) { |
| 302 | result = 0; |
| 303 | /* Wait 1s or until the new cpu calls in */ |
| 304 | for(count = 0; count < 100000 ; count++) { |
| 305 | if (secondary_stack == 0) { |
| 306 | result = 1; |
| 307 | break; |
| 308 | } |
| 309 | udelay(10); |
Jonathan A. Kollasch | 98fc2e9 | 2015-07-15 11:27:18 -0500 | [diff] [blame] | 310 | } |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 311 | } |
| 312 | secondary_stack = 0; |
| 313 | spin_unlock(&start_cpu_lock); |
| 314 | return result; |
| 315 | } |
| 316 | |
| 317 | #if CONFIG_AP_IN_SIPI_WAIT |
| 318 | |
| 319 | /** |
Stefan Reinauer | 1bfbbc0 | 2012-06-07 14:00:07 -0700 | [diff] [blame] | 320 | * Sending INIT IPI to self is equivalent of asserting #INIT with a bit of |
| 321 | * delay. |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 322 | * An undefined number of instruction cycles will complete. All global locks |
| 323 | * must be released before INIT IPI and no printk is allowed after this. |
| 324 | * De-asserting INIT IPI is a no-op on later Intel CPUs. |
| 325 | * |
| 326 | * If you set DEBUG_HALT_SELF to 1, printk's after INIT IPI are enabled |
| 327 | * but running thread may halt without releasing the lock and effectively |
| 328 | * deadlock other CPUs. |
| 329 | */ |
| 330 | #define DEBUG_HALT_SELF 0 |
| 331 | |
| 332 | /** |
| 333 | * Normally this function is defined in lapic.h as an always inline function |
| 334 | * that just keeps the CPU in a hlt() loop. This does not work on all CPUs. |
| 335 | * I think all hyperthreading CPUs might need this version, but I could only |
| 336 | * verify this on the Intel Core Duo |
| 337 | */ |
| 338 | void stop_this_cpu(void) |
| 339 | { |
Sven Schnelle | 042c146 | 2012-06-17 10:32:55 +0200 | [diff] [blame] | 340 | int timeout; |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 341 | unsigned long send_status; |
| 342 | unsigned long id; |
| 343 | |
| 344 | id = lapic_read(LAPIC_ID) >> 24; |
| 345 | |
| 346 | printk(BIOS_DEBUG, "CPU %ld going down...\n", id); |
| 347 | |
| 348 | /* send an LAPIC INIT to myself */ |
| 349 | lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id)); |
Stefan Reinauer | 1bfbbc0 | 2012-06-07 14:00:07 -0700 | [diff] [blame] | 350 | lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | |
| 351 | LAPIC_INT_ASSERT | LAPIC_DM_INIT); |
Stefan Reinauer | 6852406 | 2008-08-02 15:15:23 +0000 | [diff] [blame] | 352 | |
| 353 | /* wait for the ipi send to finish */ |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 354 | #if DEBUG_HALT_SELF |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 355 | printk(BIOS_SPEW, "Waiting for send to finish...\n"); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 356 | #endif |
Stefan Reinauer | 6852406 | 2008-08-02 15:15:23 +0000 | [diff] [blame] | 357 | timeout = 0; |
| 358 | do { |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 359 | #if DEBUG_HALT_SELF |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 360 | printk(BIOS_SPEW, "+"); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 361 | #endif |
Stefan Reinauer | 6852406 | 2008-08-02 15:15:23 +0000 | [diff] [blame] | 362 | udelay(100); |
| 363 | send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; |
| 364 | } while (send_status && (timeout++ < 1000)); |
| 365 | if (timeout >= 1000) { |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 366 | #if DEBUG_HALT_SELF |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 367 | printk(BIOS_ERR, "timed out\n"); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 368 | #endif |
Stefan Reinauer | 6852406 | 2008-08-02 15:15:23 +0000 | [diff] [blame] | 369 | } |
| 370 | mdelay(10); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 371 | |
| 372 | #if DEBUG_HALT_SELF |
| 373 | printk(BIOS_SPEW, "Deasserting INIT.\n"); |
| 374 | #endif |
| 375 | /* Deassert the LAPIC INIT */ |
| 376 | lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id)); |
| 377 | lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); |
| 378 | |
| 379 | #if DEBUG_HALT_SELF |
| 380 | printk(BIOS_SPEW, "Waiting for send to finish...\n"); |
| 381 | #endif |
| 382 | timeout = 0; |
| 383 | do { |
| 384 | #if DEBUG_HALT_SELF |
| 385 | printk(BIOS_SPEW, "+"); |
| 386 | #endif |
| 387 | udelay(100); |
| 388 | send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; |
| 389 | } while (send_status && (timeout++ < 1000)); |
| 390 | if (timeout >= 1000) { |
| 391 | #if DEBUG_HALT_SELF |
| 392 | printk(BIOS_ERR, "timed out\n"); |
| 393 | #endif |
| 394 | } |
| 395 | |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 396 | halt(); |
Stefan Reinauer | 6852406 | 2008-08-02 15:15:23 +0000 | [diff] [blame] | 397 | } |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 398 | #endif |
Stefan Reinauer | 6852406 | 2008-08-02 15:15:23 +0000 | [diff] [blame] | 399 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 400 | /* C entry point of secondary cpus */ |
Stefan Reinauer | 399486e | 2012-12-06 13:54:29 -0800 | [diff] [blame] | 401 | void asmlinkage secondary_cpu_init(unsigned int index) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 402 | { |
Sven Schnelle | 042c146 | 2012-06-17 10:32:55 +0200 | [diff] [blame] | 403 | atomic_inc(&active_cpus); |
Kyösti Mälkki | 5c3f384 | 2014-05-08 15:27:15 +0300 | [diff] [blame] | 404 | |
| 405 | if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) |
| 406 | spin_lock(&start_cpu_lock); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 407 | |
| 408 | #ifdef __SSE3__ |
| 409 | /* |
| 410 | * Seems that CR4 was cleared when AP start via lapic_start_cpu() |
| 411 | * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled |
| 412 | */ |
| 413 | u32 cr4_val; |
Aaron Durbin | 029aaf6 | 2013-10-10 12:41:49 -0500 | [diff] [blame] | 414 | cr4_val = read_cr4(); |
| 415 | cr4_val |= (CR4_OSFXSR | CR4_OSXMMEXCPT); |
| 416 | write_cr4(cr4_val); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 417 | #endif |
Ronald G. Minnich | 8b93059 | 2012-06-05 14:41:27 -0700 | [diff] [blame] | 418 | cpu_initialize(index); |
Kyösti Mälkki | 5c3f384 | 2014-05-08 15:27:15 +0300 | [diff] [blame] | 419 | |
| 420 | if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) |
| 421 | spin_unlock(&start_cpu_lock); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 422 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 423 | atomic_dec(&active_cpus); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 424 | |
| 425 | stop_this_cpu(); |
| 426 | } |
| 427 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 428 | static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu) |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 429 | { |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 430 | struct device *cpu; |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 431 | /* Loop through the cpus once getting them started */ |
| 432 | |
| 433 | for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { |
| 434 | if (cpu->path.type != DEVICE_PATH_APIC) { |
| 435 | continue; |
| 436 | } |
Kyösti Mälkki | 5c3f384 | 2014-05-08 15:27:15 +0300 | [diff] [blame] | 437 | |
| 438 | if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT) && (cpu==bsp_cpu)) |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 439 | continue; |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 440 | |
| 441 | if (!cpu->enabled) { |
| 442 | continue; |
| 443 | } |
| 444 | |
| 445 | if (cpu->initialized) { |
| 446 | continue; |
| 447 | } |
| 448 | |
| 449 | if (!start_cpu(cpu)) { |
| 450 | /* Record the error in cpu? */ |
| 451 | printk(BIOS_ERR, "CPU 0x%02x would not start!\n", |
| 452 | cpu->path.apic.apic_id); |
| 453 | } |
Kyösti Mälkki | 5c3f384 | 2014-05-08 15:27:15 +0300 | [diff] [blame] | 454 | |
| 455 | if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) |
| 456 | udelay(10); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 457 | } |
| 458 | |
Yinghai Lu | 9a8e36d | 2006-05-18 17:02:17 +0000 | [diff] [blame] | 459 | } |
| 460 | |
Damien Zammit | 149c4c5 | 2015-11-28 21:27:05 +1100 | [diff] [blame] | 461 | static void smm_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) |
| 462 | { |
| 463 | device_t cpu; |
| 464 | int pre_count = atomic_read(&active_cpus); |
| 465 | |
| 466 | /* Loop through the cpus once to let them run through SMM relocator */ |
| 467 | |
| 468 | for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { |
| 469 | if (cpu->path.type != DEVICE_PATH_APIC) { |
| 470 | continue; |
| 471 | } |
| 472 | |
| 473 | printk(BIOS_ERR, "considering CPU 0x%02x for SMM init\n", |
| 474 | cpu->path.apic.apic_id); |
| 475 | |
| 476 | if (cpu == bsp_cpu) |
| 477 | continue; |
| 478 | |
| 479 | if (!cpu->enabled) { |
| 480 | continue; |
| 481 | } |
| 482 | |
| 483 | if (!start_cpu(cpu)) { |
| 484 | /* Record the error in cpu? */ |
| 485 | printk(BIOS_ERR, "CPU 0x%02x would not start!\n", |
| 486 | cpu->path.apic.apic_id); |
| 487 | } |
| 488 | |
| 489 | /* FIXME: endless loop */ |
| 490 | while (atomic_read(&active_cpus) != pre_count) ; |
| 491 | } |
| 492 | } |
| 493 | |
Yinghai Lu | 9a8e36d | 2006-05-18 17:02:17 +0000 | [diff] [blame] | 494 | static void wait_other_cpus_stop(struct bus *cpu_bus) |
| 495 | { |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 496 | struct device *cpu; |
Yinghai Lu | 9a8e36d | 2006-05-18 17:02:17 +0000 | [diff] [blame] | 497 | int old_active_count, active_count; |
Stefan Reinauer | 2bdfb48 | 2012-04-03 16:17:11 -0700 | [diff] [blame] | 498 | long loopcount = 0; |
Ronald G. Minnich | 000bf83c | 2012-06-06 13:00:24 -0700 | [diff] [blame] | 499 | int i; |
Stefan Reinauer | 2bdfb48 | 2012-04-03 16:17:11 -0700 | [diff] [blame] | 500 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 501 | /* Now loop until the other cpus have finished initializing */ |
| 502 | old_active_count = 1; |
| 503 | active_count = atomic_read(&active_cpus); |
| 504 | while(active_count > 1) { |
| 505 | if (active_count != old_active_count) { |
Stefan Reinauer | 1bfbbc0 | 2012-06-07 14:00:07 -0700 | [diff] [blame] | 506 | printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", |
| 507 | active_count - 1); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 508 | old_active_count = active_count; |
| 509 | } |
| 510 | udelay(10); |
| 511 | active_count = atomic_read(&active_cpus); |
Stefan Reinauer | 2bdfb48 | 2012-04-03 16:17:11 -0700 | [diff] [blame] | 512 | loopcount++; |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 513 | } |
Eric Biederman | 7003ba4 | 2004-10-16 06:20:29 +0000 | [diff] [blame] | 514 | for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 515 | if (cpu->path.type != DEVICE_PATH_APIC) { |
| 516 | continue; |
| 517 | } |
Stefan Reinauer | 2bdfb48 | 2012-04-03 16:17:11 -0700 | [diff] [blame] | 518 | if (cpu->path.apic.apic_id == SPEEDSTEP_APIC_MAGIC) { |
| 519 | continue; |
| 520 | } |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 521 | if (!cpu->initialized) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 522 | printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n", |
Stefan Reinauer | 2b34db8 | 2009-02-28 20:10:20 +0000 | [diff] [blame] | 523 | cpu->path.apic.apic_id); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 524 | } |
| 525 | } |
Stefan Reinauer | 2bdfb48 | 2012-04-03 16:17:11 -0700 | [diff] [blame] | 526 | printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); |
Timothy Pearson | 6b6c653 | 2015-09-05 19:31:20 -0500 | [diff] [blame] | 527 | checkstack(_estack, 0); |
Stefan Reinauer | 75dbc38 | 2012-10-15 15:19:43 -0700 | [diff] [blame] | 528 | for(i = 1; i <= last_cpu_index; i++) |
| 529 | checkstack((void *)stacks[i] + CONFIG_STACK_SIZE, i); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 530 | } |
| 531 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 532 | #endif /* CONFIG_SMP */ |
| 533 | |
Eric Biederman | 7003ba4 | 2004-10-16 06:20:29 +0000 | [diff] [blame] | 534 | void initialize_cpus(struct bus *cpu_bus) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 535 | { |
| 536 | struct device_path cpu_path; |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 537 | struct cpu_info *info; |
| 538 | |
| 539 | /* Find the info struct for this cpu */ |
| 540 | info = cpu_info(); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 541 | |
| 542 | #if NEED_LAPIC == 1 |
| 543 | /* Ensure the local apic is enabled */ |
| 544 | enable_lapic(); |
| 545 | |
| 546 | /* Get the device path of the boot cpu */ |
| 547 | cpu_path.type = DEVICE_PATH_APIC; |
Stefan Reinauer | 2b34db8 | 2009-02-28 20:10:20 +0000 | [diff] [blame] | 548 | cpu_path.apic.apic_id = lapicid(); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 549 | #else |
| 550 | /* Get the device path of the boot cpu */ |
Eric Biederman | a9e632c | 2004-11-18 22:38:08 +0000 | [diff] [blame] | 551 | cpu_path.type = DEVICE_PATH_CPU; |
Stefan Reinauer | 2b34db8 | 2009-02-28 20:10:20 +0000 | [diff] [blame] | 552 | cpu_path.cpu.id = 0; |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 553 | #endif |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 554 | |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 555 | /* Find the device structure for the boot cpu */ |
| 556 | info->cpu = alloc_find_dev(cpu_bus, &cpu_path); |
| 557 | |
Ronald G. Minnich | 000bf83c | 2012-06-06 13:00:24 -0700 | [diff] [blame] | 558 | #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 |
Stefan Reinauer | 1bfbbc0 | 2012-06-07 14:00:07 -0700 | [diff] [blame] | 559 | // why here? In case some day we can start core1 in amd_sibling_init |
| 560 | copy_secondary_start_to_lowest_1M(); |
Yinghai Lu | 3a68aeb | 2006-01-09 20:42:50 +0000 | [diff] [blame] | 561 | #endif |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 562 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 563 | #if CONFIG_HAVE_SMI_HANDLER |
Damien Zammit | 149c4c5 | 2015-11-28 21:27:05 +1100 | [diff] [blame] | 564 | if (!IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION)) |
| 565 | smm_init(); |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 566 | #endif |
| 567 | |
Ronald G. Minnich | 000bf83c | 2012-06-06 13:00:24 -0700 | [diff] [blame] | 568 | #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 569 | /* start all aps at first, so we can init ECC all together */ |
Kyösti Mälkki | 5c3f384 | 2014-05-08 15:27:15 +0300 | [diff] [blame] | 570 | if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) |
| 571 | start_other_cpus(cpu_bus, info->cpu); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 572 | #endif |
| 573 | |
Zheng Bao | d4c5c44 | 2010-02-20 09:38:16 +0000 | [diff] [blame] | 574 | /* Initialize the bootstrap processor */ |
Ronald G. Minnich | 8b93059 | 2012-06-05 14:41:27 -0700 | [diff] [blame] | 575 | cpu_initialize(0); |
Yinghai Lu | 9a8e36d | 2006-05-18 17:02:17 +0000 | [diff] [blame] | 576 | |
Ronald G. Minnich | 000bf83c | 2012-06-06 13:00:24 -0700 | [diff] [blame] | 577 | #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 |
Kyösti Mälkki | 5c3f384 | 2014-05-08 15:27:15 +0300 | [diff] [blame] | 578 | if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) |
| 579 | start_other_cpus(cpu_bus, info->cpu); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 580 | |
Yinghai Lu | 9a8e36d | 2006-05-18 17:02:17 +0000 | [diff] [blame] | 581 | /* Now wait the rest of the cpus stop*/ |
| 582 | wait_other_cpus_stop(cpu_bus); |
| 583 | #endif |
Damien Zammit | 149c4c5 | 2015-11-28 21:27:05 +1100 | [diff] [blame] | 584 | |
| 585 | if (IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION)) { |
| 586 | /* At this point, all APs are sleeping: |
| 587 | * smm_init() will queue a pending SMI on all cpus |
| 588 | * and smm_other_cpus() will start them one by one */ |
| 589 | smm_init(); |
| 590 | #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 |
| 591 | last_cpu_index = 0; |
| 592 | smm_other_cpus(cpu_bus, info->cpu); |
| 593 | #endif |
| 594 | } |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 595 | } |