blob: 2c87cc5b5fe21061b4b814a245ad484aa441be1a [file] [log] [blame]
Uwe Hermann5211a702010-09-27 17:53:17 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Uwe Hermann5211a702010-09-27 17:53:17 +000014 */
Eric Biedermanfcd5ace2004-10-14 19:29:29 +000015
Uwe Hermann5211a702010-09-27 17:53:17 +000016__fpu_start:
17 /* Preserve BIST. */
18 movl %eax, %ebp
19
20 /*
21 * Clear the CR0[2] bit (the "Emulation" flag, EM).
22 *
23 * This indicates that the processor has an (internal or external)
24 * x87 FPU, i.e. floating point operations will be executed by the
25 * hardware (and not emulated in software).
26 *
27 * Additionally, if this bit is not cleared, MMX/SSE instructions won't
28 * work, i.e., they will trigger an invalid opcode exception (#UD).
29 */
Eric Biedermanfcd5ace2004-10-14 19:29:29 +000030 movl %cr0, %eax
Uwe Hermann5211a702010-09-27 17:53:17 +000031 andl $~(1 << 2), %eax
Eric Biedermanfcd5ace2004-10-14 19:29:29 +000032 movl %eax, %cr0
33
Uwe Hermann5211a702010-09-27 17:53:17 +000034 /* Restore BIST. */
35 movl %ebp, %eax